commit | 0e43b917e07fa536d300604632f94899f95cbdad | [log] [tgz] |
---|---|---|
author | Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> | Fri Jan 07 16:44:51 2022 +0530 |
committer | Commit Bot <commit-bot@chromium.org> | Thu Jan 20 08:25:33 2022 +0000 |
tree | a55878c0e89befc167e045e11feb4fe08a29102a | |
parent | e97f380389bc79eb4f464850cd0a8ebe6e45a1de [diff] |
UPSTREAM: mb/intel/adlrvp: Add wake events for AC connect/disconnect Enable S3/S0ix wake events for AC connect/disconnect on Alder Lake RVP. BUG=None BRANCH=None TEST=Verify board wakes from S0ix on AC connect/disconnect. Change-Id: I0d5db8161781e5e7bf12249fa3aa8a32be4bfccc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Original-Commit-Id: ba9183245fb42232132ddb5df804b8b8b5e76b82 Original-Change-Id: Iaf92821fd69a59624e58cb8af3896e2b6998723f Original-Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/60897 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3399995 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.