mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/B
During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is
copied to CSE_RW, so the sizes of these regions need to match.
BUG=b:189177538
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
GitOrigin-RevId: 6d27905e039fcf8671f6b761665cb35fb148548f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3272304
Tested-by: Copybara Service <copybara-worker-blackhole@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
diff --git a/src/mainboard/intel/adlrvp/chromeos.fmd b/src/mainboard/intel/adlrvp/chromeos.fmd
index 84adad9..53469de 100644
--- a/src/mainboard/intel/adlrvp/chromeos.fmd
+++ b/src/mainboard/intel/adlrvp/chromeos.fmd
@@ -15,7 +15,7 @@
VBLOCK_A 64K
FW_MAIN_A(CBFS)
RW_FWID_A 64
- ME_RW_A(CBFS) 4032K
+ ME_RW_A(CBFS) 3520K
}
RW_LEGACY(CBFS) 1M
RW_MISC 1M {
@@ -39,7 +39,7 @@
VBLOCK_B 64K
FW_MAIN_B(CBFS)
RW_FWID_B 64
- ME_RW_B(CBFS) 4032K
+ ME_RW_B(CBFS) 3520K
}
# Make WP_RO region align with SPI vendor
# memory protected range specification.
