| /* SPDX-License-Identifier: GPL-2.0-only */ |
| |
| #ifndef SOC_MEDIATEK_MT8195_HDMI_H |
| #define SOC_MEDIATEK_MT8195_HDMI_H |
| |
| #define HDMI_TX_BASE_REG 0x11D5F000 |
| #define HDMI_RX_BASE_REG 0x11D60000 |
| |
| #define HDMI_PROTECT_REG (HDMI_TX_BASE_REG + 0xD0) |
| |
| #define HDMI_RX_PDN_0_REG (HDMI_RX_BASE_REG + 0x464) |
| #define HDMI_RX_PDN_1_REG (HDMI_RX_BASE_REG + 0x564) |
| #define HDMI_RX_PDN_2_REG (HDMI_RX_BASE_REG + 0x468) |
| #define HDMI_RX_PDN_3_REG (HDMI_RX_BASE_REG + 0x568) |
| #define HDMI_RX_PDN_4_REG (HDMI_RX_BASE_REG + 0x46c) |
| #define HDMI_RX_PDN_5_REG (HDMI_RX_BASE_REG + 0x56c) |
| #define HDMI_RX_PDN_6_REG (HDMI_RX_BASE_REG + 0x2000) |
| #define HDMI_RX_PDN_7_REG (HDMI_RX_BASE_REG + 0x2080) |
| #define HDMI_TX_PDN_REG (HDMI_TX_BASE_REG + 0x40) |
| |
| #define HDMI_RX_PDN_0_VAL 0xFFFFFC00 |
| #define HDMI_RX_PDN_1_VAL 0xFFFFFC00 |
| #define HDMI_RX_PDN_2_VAL 0xFFFFFFFF |
| #define HDMI_RX_PDN_3_VAL 0xFFFFFFFF |
| #define HDMI_RX_PDN_4_VAL 0xFFFF000F |
| #define HDMI_RX_PDN_5_VAL 0xFFFF000F |
| #define HDMI_RX_PDN_6_VAL 0xFFFF0006 |
| #define HDMI_RX_PDN_7_VAL 0xFFFF0007 |
| #define HDMI_TX_PDN_VAL 0x0012C561 |
| |
| void hdmi_low_power_setting(void); |
| |
| #endif |
