commit b1a770db496255a3d8ce02f732271477524ebf8d
author Rex-BC Chen <rex-bc.chen@mediatek.com> Mon May 10 19:50:01 2021 +0800
committer Commit Bot <commit-bot@chromium.org> Fri May 14 18:33:24 2021 +0000
tree 6d6512d65f1927681af4d6f5f6f4d45760676a69
parent cd78498721bc0829d8901abbe86beb7fb13547ec

UPSTREAM: mb/google/cherry: Add DRAM calibration support

Initialize and calibrate DRAM in romstage.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ibdea4e49c08cbd05b335a3a782bfa53d29a988f7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c51a54ecddc08187ac9b77498fb8df5b4f82ea1e
Original-Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Original-Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2897215
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>

src/mainboard/google/cherry/Makefile.inc

diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc
index 4720dc5..a0862d3 100644
--- a/src/mainboard/google/cherry/Makefile.inc
+++ b/src/mainboard/google/cherry/Makefile.inc
@@ -7,10 +7,13 @@
 verstage-y += reset.c
 
 romstage-y += memlayout.ld
+romstage-y += boardid.c
 romstage-y += chromeos.c
 romstage-y += romstage.c
+romstage-y += sdram_configs.c
 
 ramstage-y += memlayout.ld
+ramstage-y += boardid.c
 ramstage-y += chromeos.c
 ramstage-y += mainboard.c
 ramstage-y += reset.c

src/mainboard/google/cherry/boardid.c

diff --git a/src/mainboard/google/cherry/boardid.c b/src/mainboard/google/cherry/boardid.c
new file mode 100644
index 0000000..34d7692
--- /dev/null
+++ b/src/mainboard/google/cherry/boardid.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+
+uint32_t ram_code(void)
+{
+	return 0;
+}

src/mainboard/google/cherry/romstage.c

diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c
index ec7e4f9..5505d8a 100644
--- a/src/mainboard/google/cherry/romstage.c
+++ b/src/mainboard/google/cherry/romstage.c
@@ -2,6 +2,7 @@
 
 #include <arch/stages.h>
 #include <soc/clkbuf.h>
+#include <soc/emi.h>
 #include <soc/mt6315.h>
 #include <soc/mt6359p.h>
 #include <soc/pmif.h>
@@ -15,5 +16,6 @@
 	mt6315_init();
 	clk_buf_init();
 	rtc_boot();
+	mtk_dram_init();
 	scp_rsi_enable();
 }

src/mainboard/google/cherry/sdram_configs.c

diff --git a/src/mainboard/google/cherry/sdram_configs.c b/src/mainboard/google/cherry/sdram_configs.c
new file mode 100644
index 0000000..de6bdd1
--- /dev/null
+++ b/src/mainboard/google/cherry/sdram_configs.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/dramc_param.h>
+
+const struct sdram_info *get_sdram_config(void)
+{
+	/*
+	 * The MT8195 platform supports "dram adaptive" feature to
+	 * automatically detect dram information, including channel, rank, die size...,
+	 * and can automatically configure EMI settings.
+	 * So we will be passing a placeholder param blob.
+	 */
+	static struct sdram_info params;
+	return &params;
+}