commit | e47fb6a713d8dabad8ef877cf31f70e32bb9c409 | [log] [tgz] |
---|---|---|
author | Michał Żygowski <michal.zygowski@3mdeb.com> | Sun May 09 13:54:09 2021 +0200 |
committer | Commit Bot <commit-bot@chromium.org> | Wed May 12 16:15:16 2021 +0000 |
tree | 7826e32d6e0067316efed6751f26749cece9dc00 | |
parent | ebf9a1abc8aedb44744fdb5410d976b302583fb2 [diff] |
UPSTREAM: nb/amd/pi/00730F01: Use generic allocation functions for northbridge Remove obsolete resource assigning functions. IO and MMIO address registers are currently set by amd_initcpuio to cover whole PCI hole under 4G to MMIO and IO 0x0000-0xFFFF is configured to be routed to southbridge already. Use generic PCI and resource allocation functions wherever possible to set northbridge resources. TEST=boot Debian with Linux 4.14 on apu2 4GB ECC and apu3 2GB no ECC Change-Id: I3aee3c250f37d39b7645a8c896b2ba2e6589a5d4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: fb198c6b018d715a66096859ed089d0eef0cdf2d Original-Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Original-Change-Id: I8dd5e40bce513c5ba7f1d42a06e7ab0846666942 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/52926 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2892194 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.