UPSTREAM: drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1
Not all FSPs based on FSP 2.1 supports the feature of external PPI
interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE.
Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is
selected.
Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake).
BUG=none
BRANCH=none
TEST=none
Change-Id: Id16d8c8d45de27b474611ece0afbd49a1394006e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 01e38559c36e5ca9e1cf69c7a674bf10aa156dd9
Original-Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7
Original-Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2266716
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index fc1eaf6..3caa04a 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -11,12 +11,10 @@
default n
select PLATFORM_USES_FSP2_0
select FSP_USES_CB_STACK
- select FSP_PEIM_TO_PEIM_INTERFACE
help
Include FSP 2.1 wrappers and functionality.
- Features added into FSP 2.1 specification that impacts coreboot are:
+ Feature added into FSP 2.1 specification that impacts coreboot is:
1. Remove FSP stack switch and use the same stack with boot firmware
- 2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE
config PLATFORM_USES_FSP2_2
bool
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 8cc572d..3c29b24 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -61,7 +61,7 @@
config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
bool "Perform MP Initialization by FSP using coreboot MP PPI service"
depends on FSP_USES_MP_SERVICES_PPI
- default y if PLATFORM_USES_FSP2_1
+ default y if FSP_PEIM_TO_PEIM_INTERFACE
default n
help
This option allows FSP to make use of MP services PPI published by
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 83a62ca..f58aa33 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -31,6 +31,7 @@
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1
+ select FSP_PEIM_TO_PEIM_INTERFACE
select REG_SCRIPT
select SMP
select PMC_GLOBAL_RESET_ENABLE_LOCK
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 72b0c5e..89bbdd3 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -33,6 +33,7 @@
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1
+ select FSP_PEIM_TO_PEIM_INTERFACE
select REG_SCRIPT
select SMP
select PMC_GLOBAL_RESET_ENABLE_LOCK
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index f502940..c30519c 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -33,6 +33,7 @@
select PARALLEL_MP_AP_WORK
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_1
+ select FSP_PEIM_TO_PEIM_INTERFACE
select REG_SCRIPT
select SMP
select PMC_GLOBAL_RESET_ENABLE_LOCK
