blob: 39228f45a9c01d36e88a0153ed3a0aca5f8b9f62 [file] [log] [blame]
config BOARD_GOOGLE_BASEBOARD_DRAGONEGG
def_bool n
select BOARD_ROMSIZE_KB_32768
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_ICELAKE
if BOARD_GOOGLE_BASEBOARD_DRAGONEGG
config CHROMEOS
bool
default y
select GBB_FLAG_FORCE_MANUAL_RECOVERY
config DEVICETREE
string
default "variants/baseboard/devicetree.cb"
config DIMM_SPD_SIZE
int
default 512
# Select this option to enable use of cr50 SPI TPM on dragon egg.
config DRAGONEGG_USE_SPI_TPM
bool
default y
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
config DRIVER_TPM_SPI_BUS
depends on DRAGONEGG_USE_SPI_TPM
default 0x1
config GBB_HWID
string
depends on CHROMEOS
default "DRAGONEGG TEST 1394"
config MAINBOARD_DIR
string
default "google/dragonegg"
config MAINBOARD_PART_NUMBER
string
default "Dragonegg"
config MAINBOARD_VENDOR
string
default "Google"
config MAINBOARD_FAMILY
string
default "Google_Dragonegg"
config MAX_CPUS
int
default 8
config TPM_TIS_ACPI_INTERRUPT
int
default 48 # GPE0_DW1_16 (GPP_D16)
config VARIANT_DIR
string
default "dragonegg" if BOARD_GOOGLE_DRAGONEGG
config UART_FOR_CONSOLE
int
default 0
config VBOOT
select VBOOT_LID_SWITCH
select EC_GOOGLE_CHROMEEC_SWITCHES
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
endif # BOARD_GOOGLE_BASEBOARD_DRAGONEGG