mb/google/zork: Configure GPIO_40 as drive low in sleep path
This change configures GPIO_40 (NVME_AUX_RESET_L) as drive low in
sleep path so that the PERST# to NVMe device keeps asserted until
coreboot reconfigures it as high on S3 resume path. This is similar to
the earlier change for PCIE_RST1_L but helps platforms that use
NVME_AUX_RESET_L instead of PCIE_RST1_L. GPIO_40 lives in S5 domain,
hence it retains state across S3 entry/exit.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie79e946eee8f393863630226ae2183e653030415
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261117
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index 1dd2dd5..aacf14b 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -36,6 +36,8 @@
PAD_GPO(GPIO_5, LOW),
/* PCIE_RST1_L */
PAD_GPO(GPIO_27, LOW),
+ /* NVME_AUX_RESET_L */
+ PAD_GPO(GPIO_40, LOW),
/* EN_PWR_CAMERA */
PAD_GPO(GPIO_76, LOW),
};
