| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2017 Advanced Micro Devices, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| /* PCIe Devices, Methods, Named Objects, more */ |
| #include "pci0.asl" |
| |
| /* Describe PCI INT[A-H] for the Southbridge */ |
| #include "pci_int.asl" |
| |
| /* Non-PCIe Devices */ |
| #include "fch.asl" |
