Zork: Reorganizing ACPI and adding PCI bridge configs
ACPI for Zork is mostly stoneyridge code that tried to organize by
southbridge/northbridge, but that division isn't always clear.
Refactored ACPI to more closely match the device tree to improve
organization while adding ACPI configuration for PCI bridges.
BUG=b:149838359
TEST=emerge-zork coreboot-zork chromeos-bootimage
flash on new image
check firmware_node presence and bridge routing in sysfs
Signed-off-by: Pranay Shoroff <pshoroff@google.com>
Change-Id: I1e2095567525f302dfd0bce8e39001250523180b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536
Tested-by: Pranay Shoroff <pshoroff@google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: Pranay Shoroff <pshoroff@google.com>
diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c
index 2575e6e..3cc8ffc 100644
--- a/src/mainboard/google/zork/mainboard.c
+++ b/src/mainboard/google/zork/mainboard.c
@@ -82,15 +82,15 @@
* device/slot level, not the function level.
*/
static const struct pirq_struct mainboard_pirq_data[] = {
- { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 0
- { PCIE1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi
- { PCIE2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD
- { PCIE3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 3
- { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 4
- { PCIE5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 5
- { PCIE6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME
- { PCIE7_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge to Bus A
- { PCIE8_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge to Bus B
+ { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 0
+ { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi
+ { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD
+ { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 3
+ { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 4
+ { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 5
+ { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME
+ { PCIE_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge to Bus A
+ { PCIE_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge to Bus B
{ SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
};
diff --git a/src/soc/amd/picasso/acpi/fch.asl b/src/soc/amd/picasso/acpi/fch.asl
new file mode 100644
index 0000000..8f79743
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/fch.asl
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* Describe the devices in the Southbridge */
+#include <sb_fch.asl>
+
+/* Add GPIO library */
+#include <soc/amd/common/acpi/gpio_bank_lib.asl>
\ No newline at end of file
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl
deleted file mode 100644
index 2759447..0000000
--- a/src/soc/amd/picasso/acpi/northbridge.asl
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- * Copyright (C) 2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Note: Only need HID on Primary Bus */
-External (TOM1)
-External (TOM2)
-Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
-Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
-
-/* Describe the Northbridge devices */
-
-Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
-{
- Return(Zero)
-}
-
-Method(_STA, 0, NotSerialized)
-{
- Return(0x0B) /* Status is visible */
-}
-
-/* PCI Routing Table */
-Name(PR0, Package(){
- /* Bus 0, Dev 0x00 - F2: IOMMU */
- Package() { 0x0000FFFF, 0, INTA, 0 },
- Package() { 0x0000FFFF, 0, INTB, 0 },
- Package() { 0x0000FFFF, 0, INTC, 0 },
- Package() { 0x0000FFFF, 0, INTD, 0 },
-
- /* Bus 0, Dev 0x01 - F[1-7]: GPP PCI Bridge */
- Package() { 0x0001FFFF, 0, INTA, 0 },
- Package() { 0x0001FFFF, 1, INTB, 0 },
- Package() { 0x0001FFFF, 2, INTC, 0 },
- Package() { 0x0001FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 0x08 - F1:PCI Bridge to Bus A, F2: PCI Bridge to Bus B */
- Package() { 0x0008FFFF, 0, INTA, 0 },
- Package() { 0x0008FFFF, 1, INTB, 0 },
- Package() { 0x0008FFFF, 2, INTC, 0 },
- Package() { 0x0008FFFF, 3, INTD, 0 },
-
- /* Bus 0, Dev 0x14 - F0:SMBus F3:LPC */
- Package() { 0x0014FFFF, 0, INTA, 0 },
- Package() { 0x0014FFFF, 1, INTB, 0 },
- Package() { 0x0014FFFF, 2, INTC, 0 },
- Package() { 0x0014FFFF, 3, INTD, 0 },
-})
-
-Method(_PRT,0, NotSerialized)
-{
- Return(PR0)
-}
-
-Device(AMRT) {
- Name(_ADR, 0x00000000)
-} /* end AMRT */
-
-Device(PCSD) { /* Processor configuration space devices */
- Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
-}
-
-/* Internal Graphics */
-Device(IGFX) {
- Name(_ADR, 0x00010000)
-}
-
-Device(AZHD) { /* 0:9.2 - HD Audio */
- Name(_ADR, 0x00090002)
- OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- Field(AZPD, AnyAcc, NoLock, Preserve) {
- offset (0x42),
- NSDI, 1,
- NSDO, 1,
- NSEN, 1,
- offset (0x44),
- IPCR, 4,
- offset (0x54),
- PWST, 2,
- , 6,
- PMEB, 1,
- , 6,
- PMST, 1,
- offset (0x62),
- MMCR, 1,
- offset (0x64),
- MMLA, 32,
- offset (0x68),
- MMHA, 32,
- offset (0x6c),
- MMDT, 16,
- }
-
- Method (_INI, 0, NotSerialized)
- {
- If (LEqual (OSVR, 0x03))
- {
- Store (Zero, NSEN)
- Store (One, NSDO)
- Store (One, NSDI)
- }
- }
-} /* end AZHD */
diff --git a/src/soc/amd/picasso/acpi/pci0.asl b/src/soc/amd/picasso/acpi/pci0.asl
new file mode 100644
index 0000000..a742d0d
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/pci0.asl
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+Device(PCI0) {
+ /* Note: Only need HID on Primary Bus */
+ External (TOM1)
+ External (TOM2)
+ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
+ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
+
+ /* PCI Routing Table */
+ Name(PR0, Package(){
+ /* Bus 0, Dev 0x00 - F2: IOMMU */
+ Package() { 0x0000FFFF, 0, INTA, 0 },
+ Package() { 0x0000FFFF, 0, INTB, 0 },
+ Package() { 0x0000FFFF, 0, INTC, 0 },
+ Package() { 0x0000FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 0x01 - F[1-7]: GPP PCI Bridge */
+ Package() { 0x0001FFFF, 0, INTA, 0 },
+ Package() { 0x0001FFFF, 1, INTB, 0 },
+ Package() { 0x0001FFFF, 2, INTC, 0 },
+ Package() { 0x0001FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 0x08 - F1:PCI Bridge to Bus A, F2: PCI Bridge to Bus B */
+ Package() { 0x0008FFFF, 0, INTA, 0 },
+ Package() { 0x0008FFFF, 1, INTB, 0 },
+ Package() { 0x0008FFFF, 2, INTC, 0 },
+ Package() { 0x0008FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 0x14 - F0:SMBus F3:LPC */
+ Package() { 0x0014FFFF, 0, INTA, 0 },
+ Package() { 0x0014FFFF, 1, INTB, 0 },
+ Package() { 0x0014FFFF, 2, INTC, 0 },
+ Package() { 0x0014FFFF, 3, INTD, 0 },
+ })
+
+ /*************************/
+ /* Devices */
+ #include "pci0_devices.asl"
+
+ /*************************/
+ /* Methods */
+ #include "pci0_methods.asl"
+
+ /*************************/
+ /* Misc */
+ External(\_SB.ALIB, MethodObj)
+
+ /*
+ * Arg0:device:
+ * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1,
+ * 18=EHCI, 23=xHCI, 24=SD
+ * Arg1:D-state
+ */
+ Mutex (FDAS, 0) /* FCH Device AOAC Semophore */
+
+ /*************************/
+ /* Named Objects */
+ Name(CRES, ResourceTemplate() {
+ /* Set the Bus number and Secondary Bus number for the PCI0 device
+ * The Secondary bus range for PCI0 lets the system
+ * know what bus values are allowed on the downstream
+ * side of this PCI bus if there is a PCI-PCI bridge.
+ * PCI busses can have 256 secondary busses which
+ * range from [0-0xFF] but they do not need to be
+ * sequential.
+ */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x00ff, /* range maximum */
+ 0x0000, /* translation */
+ 0x0100, /* length */
+ ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
+
+ IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0cf7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0cf8 /* length */
+ )
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x03b0, /* range minimum */
+ 0x03df, /* range maximum */
+ 0x0000, /* translation */
+ 0x0030 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0d00, /* range minimum */
+ 0xffff, /* range maximum */
+ 0x0000, /* translation */
+ 0xf300 /* length */
+ )
+
+ Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+
+ /* memory space for PCI BARs below 4GB */
+ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+ }) /* End Name(_SB.PCI0.CRES) */
+
+ /*************************/
+ /* Operation Regions + Fields */
+
+ // OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000)
+ // Field( SMIC, ByteAcc, NoLock, Preserve) {
+ // /* MISC registers */
+ // offset (0x03ee),
+ // U3PS, 2, /* Usb3PowerSel */
+
+ // offset (0x0e28),
+ // ,29 ,
+ // SARP, 1, /* Sata Ref Clock Powerdown */
+ // U2RP, 1, /* Usb2 Ref Clock Powerdown */
+ // U3RP, 1, /* Usb3 Ref Clock Powerdown */
+
+ // /* AOAC Registers */
+ // offset (0x1e4a), /* I2C0 D3 Control */
+ // I0TD, 2,
+ // , 1,
+ // I0PD, 1,
+ // offset (0x1e4b), /* I2C0 D3 State */
+ // I0DS, 3,
+
+ // offset (0x1e4c), /* I2C1 D3 Control */
+ // I1TD, 2,
+ // , 1,
+ // I1PD, 1,
+ // offset (0x1e4d), /* I2C1 D3 State */
+ // I1DS, 3,
+
+ // offset (0x1e4e), /* I2C2 D3 Control */
+ // I2TD, 2,
+ // , 1,
+ // I2PD, 1,
+ // offset (0x1e4f), /* I2C2 D3 State */
+ // I2DS, 3,
+
+ // offset (0x1e50), /* I2C3 D3 Control */
+ // I3TD, 2,
+ // , 1,
+ // I3PD, 1,
+ // offset (0x1e51), /* I2C3 D3 State */
+ // I3DS, 3,
+
+ // offset (0x1e56), /* UART0 D3 Control */
+ // U0TD, 2,
+ // , 1,
+ // U0PD, 1,
+ // offset (0x1e57), /* UART0 D3 State */
+ // U0DS, 3,
+
+ // offset (0x1e58), /* UART1 D3 Control */
+ // U1TD, 2,
+ // , 1,
+ // U1PD, 1,
+ // offset (0x1e59), /* UART1 D3 State */
+ // U1DS, 3,
+
+ // offset (0x1e60), /* UART2 D3 Control */
+ // U2TD, 2,
+ // , 1,
+ // U2PD, 1,
+ // offset (0x1e61), /* UART2 D3 State */
+ // U2DS, 3,
+
+ // offset (0x1e71), /* SD D3 State */
+ // SDDS, 3,
+
+ // offset (0x1e74), /* UART3 D3 Control */
+ // U3TD, 2,
+ // , 1,
+ // U3PD, 1,
+ // offset (0x1e75), /* UART3 D3 State */
+ // U3DS, 3,
+
+ // offset (0x1e80), /* Shadow Register Request */
+ // , 15,
+ // RQ15, 1,
+ // , 2,
+ // RQ18, 1,
+ // , 4,
+ // RQ23, 1,
+ // RQ24, 1,
+ // , 5,
+ // RQTY, 1,
+ // offset (0x1e84), /* Shadow Register Status */
+ // , 15,
+ // SASR, 1, /* SATA 15 Shadow Reg Request Status Register */
+ // , 2,
+ // U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */
+ // , 4,
+ // U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */
+ // SDSR, 1, /* SD 24 Shadow Reg Request Status Register */
+
+ // offset (0x1ea0), /* PwrGood Control */
+ // PG1A, 1,
+ // PG2_, 1,
+ // ,1,
+ // U3PG, 1, /* Usb3 Power Good BIT3 */
+
+ // offset (0x1ea3), /* PwrGood Control b[31:24] */
+ // PGA3, 8 ,
+ // }
+
+ // OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000)
+ // Field(FCFG, DwordAcc, NoLock, Preserve)
+ // {
+ // /* XHCI */
+ // Offset(0x00080010), /* Base address */
+ // XHBA, 32,
+ // Offset(0x0008002c), /* Subsystem ID / Vendor ID */
+ // XH2C, 32,
+
+ // Offset(0x00080048), /* Indirect PCI Index Register */
+ // IDEX, 32,
+ // DATA, 32,
+ // Offset(0x00080054), /* PME Control / Status */
+ // U_PS, 2,
+
+ // /* EHCI */
+ // Offset(0x00090004), /* Control */
+ // , 1,
+ // EHME, 1,
+ // Offset(0x00090010), /* Base address */
+ // EHBA, 32,
+ // Offset(0x0009002c), /* Subsystem ID / Vendor ID */
+ // EH2C, 32,
+ // Offset(0x00090054), /* EHCI Spare 1 */
+ // EH54, 8,
+ // Offset(0x00090064), /* Misc Control 2 */
+ // EH64, 8,
+
+ // Offset(0x000900c4), /* PME Control / Status */
+ // E_PS, 2,
+
+ // /* LPC Bridge */
+ // Offset(0x000a30cb), /* ClientRomProtect[31:24] */
+ // , 7,
+ // AUSS, 1, /* AutoSizeStart */
+ // }
+}
\ No newline at end of file
diff --git a/src/soc/amd/picasso/acpi/pci0_devices.asl b/src/soc/amd/picasso/acpi/pci0_devices.asl
new file mode 100644
index 0000000..4ee1987
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/pci0_devices.asl
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+// 0:00.0 # Root Complex
+Device (GNB){
+ Name(_ADR, 0x00000000)
+}
+// 0:00.2 # IOMMU
+Device (IOMM){
+ Name(_ADR, 0x00000002)
+}
+// 0:01.1 # GPP Bridge 0
+Device (PBR0){
+ Name(_ADR, 0x00010001)
+}
+// 0:01.2 # GPP Bridge 1
+Device (PBR1){
+ Name(_ADR, 0x00010002)
+}
+// 0:01.3 # GPP Bridge 2
+Device (PBR2){
+ Name(_ADR, 0x00010003)
+}
+// 0:01.4 # GPP Bridge 3
+Device (PBR3){
+ Name(_ADR, 0x00010004)
+}
+// 0:01.5 # GPP Bridge 4
+Device (PBR4){
+ Name(_ADR, 0x00010005)
+}
+// 0:01.6 # GPP Bridge 5
+Device (PBR5){
+ Name(_ADR, 0x00010006)
+}
+// 0:01.7 # GPP Bridge 6
+Device (PBR6){
+ Name(_ADR, 0x00010007)
+}
+// 0:08.1 # Internal GPP Bridge 0 to Bus A
+Device (PBRA){
+ Name(_ADR, 0x00080001)
+ // 0.0 # Internal GPU
+ Device (IGFX){
+ Name(_ADR, 0x00000000)
+ }
+ // 0.1 # Display HDA
+ // 0.2 # Crypto Coprocesor
+
+ // 0.3 # XHCI 0 under Bus A
+ Device(XHC0) {
+ Name(_ADR, 0x00000003)
+ Name(_PRW, Package() { 0xb, 3 })
+
+ Method(_S0W,0) {
+ Return(0)
+ }
+
+ Method(_S3W,0) {
+ Return(4)
+ }
+
+ Method(_S4W,0) {
+ Return(4)
+ }
+
+ } /* end XHC0 */
+
+ // 0.4 # XHCI 1 under Bus A
+ Device(XHC1) {
+ Name(_ADR, 0x00000004)
+ Name(_PRW, Package() { 0xb, 3 })
+
+ Method(_S0W,0) {
+ Return(0)
+ }
+
+ Method(_S3W,0) {
+ Return(4)
+ }
+
+ Method(_S4W,0) {
+ Return(4)
+ }
+
+ } /* end XHC1 */
+
+ // 0.5 # Audio Processor
+ // 0.6 # Audio Processor - HD Audio Controller
+ Device(AZHD) {
+ Name(_ADR, 0x00000006)
+ /* Operation Region defining space in memory for audio to work in */
+ OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+ Field(AZPD, AnyAcc, NoLock, Preserve) {
+ offset (0x42),
+ NSDI, 1,
+ NSDO, 1,
+ NSEN, 1,
+ offset (0x44),
+ IPCR, 4,
+ offset (0x54),
+ PWST, 2,
+ , 6,
+ PMEB, 1,
+ , 6,
+ PMST, 1,
+ offset (0x62),
+ MMCR, 1,
+ offset (0x64),
+ MMLA, 32,
+ offset (0x68),
+ MMHA, 32,
+ offset (0x6c),
+ MMDT, 16,
+ }
+
+ Method (_INI, 0, NotSerialized)
+ {
+ If (LEqual (OSVR, 0x03))
+ {
+ Store (Zero, NSEN)
+ Store (One, NSDO)
+ Store (One, NSDI)
+ }
+ }
+ } /* end AZHD */
+ // 0.7 # non-Sensor Fusion Hub device
+}
+
+// 0:08.2 # Internal GPP Bridge 0 to Bus B
+Device (PBRB){
+ Name(_ADR, 0x00080002)
+ /* 0:00.0 - AHCI/SATA */
+ Device(STCR) {
+ Name(_ADR, 0x00000000)
+ } /* end STCR */
+}
+// 0:14.0 # SM
+Device(SBUS) {
+ Name(_ADR, 0x00140000)
+}
+// 0:14.3 # D14F3 bridge/LPC Bus
+#include <soc/amd/common/acpi/lpc.asl>
+
+//0:18.0 # Data Fabric Bus
+Device(DFBS) {
+ Name(_ADR, 0x00180000)
+}
\ No newline at end of file
diff --git a/src/soc/amd/picasso/acpi/pci0_methods.asl b/src/soc/amd/picasso/acpi/pci0_methods.asl
new file mode 100644
index 0000000..d6b35a0
--- /dev/null
+++ b/src/soc/amd/picasso/acpi/pci0_methods.asl
@@ -0,0 +1,330 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/* Operating System Capabilities Method */
+Method(_OSC,4) {
+ /* Check for proper PCI/PCIe UUID
+ * defined in "6.2.11.3 OSC Implementation Example
+ * for PCI Host Bridge Devices" of ACPI Spec v6.3 */
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ } Else {
+ CreateDWordField(Arg3,0,CDW1)
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+}
+
+Method(_CRS, 0) {
+ /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+ CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+
+ /*
+ * Declare memory between TOM1 and 4GB as available
+ * for PCI MMIO.
+ * Use ShiftLeft to avoid 64bit constant (for XP).
+ * This will work even if the OS does 32bit arithmetic, as
+ * 32bit (0x00000000 - TOM1) will wrap and give the same
+ * result as 64bit (0x100000000 - TOM1).
+ */
+ Store(TOM1, MM1B)
+ ShiftLeft(0x10000000, 4, Local0)
+ Subtract(Local0, TOM1, Local0)
+ Store(Local0, MM1L)
+
+ Return(CRES) /* note to change the Name buffer */
+} /* end of Method(_SB.PCI0._CRS) */
+
+/*
+*
+* FIRST METHOD CALLED UPON BOOT
+*
+* 1. If debugging, print current OS and ACPI interpreter.
+* 2. Get PCI Interrupt routing from ACPI VSM, this
+* value is based on user choice in BIOS setup.
+*/
+Method(_INI, 0, Serialized) {
+ /* DBGO("\\_SB\\_INI\n") */
+ /* DBGO(" DSDT.ASL code from ") */
+ /* DBGO(__DATE__) */
+ /* DBGO(" ") */
+ /* DBGO(__TIME__) */
+ /* DBGO("\n Sleep states supported: ") */
+ /* DBGO("\n") */
+ /* DBGO(" \\_OS=") */
+ /* DBGO(\_OS) */
+ /* DBGO("\n \\_REV=") */
+ /* DBGO(\_REV) */
+ /* DBGO("\n") */
+
+ /* Determine the OS we're running on */
+ OSFL()
+
+ /* Send ALIB Function 1 the AC/DC state */
+ Name(F1BF, Buffer(0x03){})
+ CreateWordField(F1BF, 0, F1SZ)
+ CreateByteField(F1BF, 2, F1DA)
+
+ Store(3, F1SZ)
+ Store(\PWRS, F1DA)
+
+ \_SB.ALIB(1, F1BF)
+
+} /* End Method(_SB._INI) */
+
+Method(OSFL, 0){
+
+ if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
+
+ if (CondRefOf(\_OSI))
+ {
+ Store(1, OSVR) /* Assume some form of XP */
+ if (\_OSI("Windows 2006")) /* Vista */
+ {
+ Store(2, OSVR)
+ }
+ } else {
+ If(WCMP(\_OS,"Linux")) {
+ Store(3, OSVR) /* Linux */
+ } Else {
+ Store(4, OSVR) /* Gotta be WinCE */
+ }
+ }
+ Return(OSVR)
+}
+
+Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
+{
+ Return(Zero)
+}
+
+Method(_STA, 0, NotSerialized)
+{
+ Return(0x0B) /* Status is visible */
+}
+
+Method(_PRT,0, NotSerialized)
+{
+ Return(PR0)
+}
+
+// Method(FDDC, 2, Serialized)
+// {
+// Acquire(FDAS, 0xffff)
+
+// if(LEqual(Arg1, 0)) {
+// Switch(ToInteger(Arg0)) {
+// Case(Package() {5, 15, 24}) {
+// Store(One, PG1A)
+// }
+// Case(Package() {6, 7, 8, 11, 12, 18}) {
+// Store(One, PG2_)
+// }
+// }
+// /* put device into D0 */
+// Switch(ToInteger(Arg0))
+// {
+// Case(5) {
+// Store(0x00, I0TD)
+// Store(One, I0PD)
+// Store(I0DS, Local0)
+// while(LNotEqual(Local0,0x7)) {
+// Store(I0DS, Local0)
+// }
+// }
+// Case(6) {
+// Store(0x00, I1TD)
+// Store(One, I1PD)
+// Store(I1DS, Local0)
+// while(LNotEqual(Local0,0x7)) {
+// Store(I1DS, Local0)
+// }
+// }
+// Case(7) {
+// Store(0x00, I2TD)
+// Store(One, I2PD)
+// Store(I2DS, Local0)
+// while(LNotEqual(Local0,0x7)) {
+// Store(I2DS, Local0)
+// }
+// }
+// Case(8) {Store(0x00, I3TD)
+// Store(One, I3PD)
+// Store(I3DS, Local0)
+// while(LNotEqual(Local0,0x7)) {
+// Store(I3DS, Local0)
+// }
+// }
+// Case(11) {
+// Store(0x00, U0TD)
+// Store(One, U0PD)
+// Store(U0DS, Local0)
+// while(LNotEqual(Local0,0x7)) {
+// Store(U0DS, Local0)
+// }
+// }
+// Case(12) {
+// Store(0x00, U1TD)
+// Store(One, U1PD)
+// Store(U1DS, Local0)
+// while(LNotEqual(Local0,0x7)) {
+// Store(U1DS, Local0)
+// }
+// }
+// Case(16) {
+// Store(0x00, U2TD)
+// Store(One, U2PD)
+// Store(U2DS, Local0)
+// while(LNotEqual(Local0,0x7)) {
+// Store(U2DS, Local0)
+// }
+// }
+// Case(26) {
+// Store(0x00, U3TD)
+// Store(One, U3PD)
+// Store(U3DS, Local0)
+// while(LNotEqual(Local0,0x7)) {
+// Store(U3DS, Local0)
+// }
+// }
+// }
+// } else {
+// /* put device into D3cold */
+// Switch(ToInteger(Arg0))
+// {
+// Case(5) {
+// Store(Zero, I0PD)
+// Store(I0DS, Local0)
+// while(LNotEqual(Local0,0x0)) {
+// Store(I0DS, Local0)
+// }
+// Store(0x03, I0TD)
+// }
+// Case(6) {
+// Store(Zero, I1PD)
+// Store(I1DS, Local0)
+// while(LNotEqual(Local0,0x0)) {
+// Store(I1DS, Local0)
+// }
+// Store(0x03, I1TD)
+// }
+// Case(7) {
+// Store(Zero, I2PD)
+// Store(I2DS, Local0)
+// while(LNotEqual(Local0,0x0)) {
+// Store(I2DS, Local0)
+// }
+// Store(0x03, I2TD)}
+// Case(8) {
+// Store(Zero, I3PD)
+// Store(I3DS, Local0)
+// while(LNotEqual(Local0,0x0)) {
+// Store(I3DS, Local0)
+// }
+// Store(0x03, I3TD)
+// }
+// Case(11) {
+// Store(Zero, U0PD)
+// Store(U0DS, Local0)
+// while(LNotEqual(Local0,0x0)) {
+// Store(U0DS, Local0)
+// }
+// Store(0x03, U0TD)
+// }
+// Case(12) {
+// Store(Zero, U1PD)
+// Store(U1DS, Local0)
+// while(LNotEqual(Local0,0x0)) {
+// Store(U1DS, Local0)
+// }
+// Store(0x03, U1TD)
+// }
+// Case(16) {
+// Store(Zero, U2PD)
+// Store(U2DS, Local0)
+// while(LNotEqual(Local0,0x0)) {
+// Store(U2DS, Local0)
+// }
+// Store(0x03, U2TD)
+// }
+// Case(26) {
+// Store(Zero, U3PD)
+// Store(U3DS, Local0)
+// while(LNotEqual(Local0,0x0)) {
+// Store(U3DS, Local0)
+// }
+// Store(0x03, U3TD)
+// }
+// }
+// if(LEqual(I1TD, 3)) {
+// if(LEqual(I2TD, 3)) {
+// if(LEqual(I3TD, 3)) {
+// if(LEqual(U0TD, 3)) {
+// if(LEqual(U1TD, 3)) {
+// Store(Zero, PG2_)
+// }
+// }
+// }
+// }
+// }
+// }
+// Release(FDAS)
+// }
+
+Method(FPTS,0, Serialized) /* FCH _PTS *//* Operating System Capabilities Method */
+
+{
+}
+
+// Method(FWAK,0, Serialized) /* FCH _WAK */
+// {
+// if(LEqual(\UT0E, zero)) {
+// if(LNotEqual(U0TD, 0x03)) {
+// FDDC(11, 3)
+// }
+// }
+// if(LEqual(\UT1E, zero)) {
+// if(LNotEqual(U1TD, 0x03)) {
+// FDDC(12, 3)
+// }
+// }
+// if(LEqual(\IC2E, zero)) {
+// if(LNotEqual(I2TD, 0x03)) {
+// FDDC(7, 3)
+// }
+// }
+// if(LEqual(\IC3E, zero)) {
+// if(LNotEqual(I3TD, 0x03)) {
+// FDDC(8, 3)
+// }
+// }
+// }
+
+/*
+* Helper for setting a bit in AOACxA0 PwrGood Control
+* Arg0: bit to set or clear
+* Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0]
+*/
+// Method(PWGC,2, Serialized)
+// {
+// And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */
+// if(Arg1) {
+// Or(Arg0, Local0, Local0)
+// } else {
+// Not(Arg0, Local1)
+// And(Local1, Local0, Local0)
+// }
+// Store(Local0, PGA3)
+// if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */
+// Store(PGA3, Local0)
+// And(Arg0, Local0, Local0)
+// while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */
+// Store(PGA3, Local0)
+// And(Arg0, Local0, Local0)
+// }
+// }
+// }
+
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
deleted file mode 100644
index bd340dd..0000000
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-External(\_SB.ALIB, MethodObj)
-
-/* System Bus */
-/* _SB.PCI0 */
-
-/* Operating System Capabilities Method */
-Method(_OSC,4)
-{
- /* Check for proper PCI/PCIe UUID */
- If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
- {
- /* Let OS control everything */
- Return (Arg3)
- } Else {
- CreateDWordField(Arg3,0,CDW1)
- Or(CDW1,4,CDW1) // Unrecognized UUID
- Return(Arg3)
- }
-}
-
-/* Describe the Southbridge devices */
-
-/* 0:11.0 - SATA */
-Device(STCR) {
- Name(_ADR, 0x00110000)
-} /* end STCR */
-
-/* 0:14.0 - SMBUS */
-Device(SBUS) {
- Name(_ADR, 0x00140000)
-} /* end SBUS */
-
-#include "usb.asl"
-
-/* 0:14.2 - I2S Audio */
-
-/* 0:14.3 - LPC */
-#include <soc/amd/common/acpi/lpc.asl>
-
-Name(CRES, ResourceTemplate() {
- /* Set the Bus number and Secondary Bus number for the PCI0 device
- * The Secondary bus range for PCI0 lets the system
- * know what bus values are allowed on the downstream
- * side of this PCI bus if there is a PCI-PCI bridge.
- * PCI busses can have 256 secondary busses which
- * range from [0-0xFF] but they do not need to be
- * sequential.
- */
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x00ff, /* range maximum */
- 0x0000, /* translation */
- 0x0100, /* length */
- ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
-
- IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0cf7, /* range maximum */
- 0x0000, /* translation */
- 0x0cf8 /* length */
- )
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x03b0, /* range minimum */
- 0x03df, /* range maximum */
- 0x0000, /* translation */
- 0x0030 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0d00, /* range minimum */
- 0xffff, /* range maximum */
- 0x0000, /* translation */
- 0xf300 /* length */
- )
-
- Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */
- Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
-
- /* memory space for PCI BARs below 4GB */
- Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-}) /* End Name(_SB.PCI0.CRES) */
-
-Method(_CRS, 0) {
- /* DBGO("\\_SB\\PCI0\\_CRS\n") */
- CreateDWordField(CRES, ^MMIO._BAS, MM1B)
- CreateDWordField(CRES, ^MMIO._LEN, MM1L)
-
- /*
- * Declare memory between TOM1 and 4GB as available
- * for PCI MMIO.
- * Use ShiftLeft to avoid 64bit constant (for XP).
- * This will work even if the OS does 32bit arithmetic, as
- * 32bit (0x00000000 - TOM1) will wrap and give the same
- * result as 64bit (0x100000000 - TOM1).
- */
- Store(TOM1, MM1B)
- ShiftLeft(0x10000000, 4, Local0)
- Subtract(Local0, TOM1, Local0)
- Store(Local0, MM1L)
-
- Return(CRES) /* note to change the Name buffer */
-} /* end of Method(_SB.PCI0._CRS) */
-
-/*
- *
- * FIRST METHOD CALLED UPON BOOT
- *
- * 1. If debugging, print current OS and ACPI interpreter.
- * 2. Get PCI Interrupt routing from ACPI VSM, this
- * value is based on user choice in BIOS setup.
- */
-Method(_INI, 0, Serialized) {
- /* DBGO("\\_SB\\_INI\n") */
- /* DBGO(" DSDT.ASL code from ") */
- /* DBGO(__DATE__) */
- /* DBGO(" ") */
- /* DBGO(__TIME__) */
- /* DBGO("\n Sleep states supported: ") */
- /* DBGO("\n") */
- /* DBGO(" \\_OS=") */
- /* DBGO(\_OS) */
- /* DBGO("\n \\_REV=") */
- /* DBGO(\_REV) */
- /* DBGO("\n") */
-
- /* Determine the OS we're running on */
- OSFL()
-
- /* Send ALIB Function 1 the AC/DC state */
- Name(F1BF, Buffer(0x03){})
- CreateWordField(F1BF, 0, F1SZ)
- CreateByteField(F1BF, 2, F1DA)
-
- Store(3, F1SZ)
- Store(\PWRS, F1DA)
-
- \_SB.ALIB(1, F1BF)
-
-} /* End Method(_SB._INI) */
-
-Method(OSFL, 0){
-
- if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
-
- if (CondRefOf(\_OSI))
- {
- Store(1, OSVR) /* Assume some form of XP */
- if (\_OSI("Windows 2006")) /* Vista */
- {
- Store(2, OSVR)
- }
- } else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
- } Else {
- Store(4, OSVR) /* Gotta be WinCE */
- }
- }
- Return(OSVR)
-}
-
-OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000)
-Field( SMIC, ByteAcc, NoLock, Preserve) {
- /* MISC registers */
- offset (0x03ee),
- U3PS, 2, /* Usb3PowerSel */
-
- offset (0x0e28),
- ,29 ,
- SARP, 1, /* Sata Ref Clock Powerdown */
- U2RP, 1, /* Usb2 Ref Clock Powerdown */
- U3RP, 1, /* Usb3 Ref Clock Powerdown */
-
- /* AOAC Registers */
- offset (0x1e4a), /* I2C0 D3 Control */
- I0TD, 2,
- , 1,
- I0PD, 1,
- offset (0x1e4b), /* I2C0 D3 State */
- I0DS, 3,
-
- offset (0x1e4c), /* I2C1 D3 Control */
- I1TD, 2,
- , 1,
- I1PD, 1,
- offset (0x1e4d), /* I2C1 D3 State */
- I1DS, 3,
-
- offset (0x1e4e), /* I2C2 D3 Control */
- I2TD, 2,
- , 1,
- I2PD, 1,
- offset (0x1e4f), /* I2C2 D3 State */
- I2DS, 3,
-
- offset (0x1e50), /* I2C3 D3 Control */
- I3TD, 2,
- , 1,
- I3PD, 1,
- offset (0x1e51), /* I2C3 D3 State */
- I3DS, 3,
-
- offset (0x1e56), /* UART0 D3 Control */
- U0TD, 2,
- , 1,
- U0PD, 1,
- offset (0x1e57), /* UART0 D3 State */
- U0DS, 3,
-
- offset (0x1e58), /* UART1 D3 Control */
- U1TD, 2,
- , 1,
- U1PD, 1,
- offset (0x1e59), /* UART1 D3 State */
- U1DS, 3,
-
- offset (0x1e60), /* UART2 D3 Control */
- U2TD, 2,
- , 1,
- U2PD, 1,
- offset (0x1e61), /* UART2 D3 State */
- U2DS, 3,
-
- offset (0x1e71), /* SD D3 State */
- SDDS, 3,
-
- offset (0x1e74), /* UART3 D3 Control */
- U3TD, 2,
- , 1,
- U3PD, 1,
- offset (0x1e75), /* UART3 D3 State */
- U3DS, 3,
-
- offset (0x1e80), /* Shadow Register Request */
- , 15,
- RQ15, 1,
- , 2,
- RQ18, 1,
- , 4,
- RQ23, 1,
- RQ24, 1,
- , 5,
- RQTY, 1,
- offset (0x1e84), /* Shadow Register Status */
- , 15,
- SASR, 1, /* SATA 15 Shadow Reg Request Status Register */
- , 2,
- U2SR, 1, /* USB2 18 Shadow Reg Request Status Register */
- , 4,
- U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */
- SDSR, 1, /* SD 24 Shadow Reg Request Status Register */
-
- offset (0x1ea0), /* PwrGood Control */
- PG1A, 1,
- PG2_, 1,
- ,1,
- U3PG, 1, /* Usb3 Power Good BIT3 */
-
- offset (0x1ea3), /* PwrGood Control b[31:24] */
- PGA3, 8 ,
-}
-
-OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000)
-Field(FCFG, DwordAcc, NoLock, Preserve)
-{
- /* XHCI */
- Offset(0x00080010), /* Base address */
- XHBA, 32,
- Offset(0x0008002c), /* Subsystem ID / Vendor ID */
- XH2C, 32,
-
- Offset(0x00080048), /* Indirect PCI Index Register */
- IDEX, 32,
- DATA, 32,
- Offset(0x00080054), /* PME Control / Status */
- U_PS, 2,
-
- /* EHCI */
- Offset(0x00090004), /* Control */
- , 1,
- EHME, 1,
- Offset(0x00090010), /* Base address */
- EHBA, 32,
- Offset(0x0009002c), /* Subsystem ID / Vendor ID */
- EH2C, 32,
- Offset(0x00090054), /* EHCI Spare 1 */
- EH54, 8,
- Offset(0x00090064), /* Misc Control 2 */
- EH64, 8,
-
- Offset(0x000900c4), /* PME Control / Status */
- E_PS, 2,
-
- /* LPC Bridge */
- Offset(0x000a30cb), /* ClientRomProtect[31:24] */
- , 7,
- AUSS, 1, /* AutoSizeStart */
-}
-
-/*
- * Arg0:device:
- * 5=I2C0, 6=I2C1, 7=I2C2, 8=I2C3, 11=UART0, 12=UART1,
- * 18=EHCI, 23=xHCI, 24=SD
- * Arg1:D-state
- */
-Mutex (FDAS, 0) /* FCH Device AOAC Semophore */
-Method(FDDC, 2, Serialized)
-{
- Acquire(FDAS, 0xffff)
-
- if(LEqual(Arg1, 0)) {
- Switch(ToInteger(Arg0)) {
- Case(Package() {5, 15, 24}) {
- Store(One, PG1A)
- }
- Case(Package() {6, 7, 8, 11, 12, 18}) {
- Store(One, PG2_)
- }
- }
- /* put device into D0 */
- Switch(ToInteger(Arg0))
- {
- Case(5) {
- Store(0x00, I0TD)
- Store(One, I0PD)
- Store(I0DS, Local0)
- while(LNotEqual(Local0,0x7)) {
- Store(I0DS, Local0)
- }
- }
- Case(6) {
- Store(0x00, I1TD)
- Store(One, I1PD)
- Store(I1DS, Local0)
- while(LNotEqual(Local0,0x7)) {
- Store(I1DS, Local0)
- }
- }
- Case(7) {
- Store(0x00, I2TD)
- Store(One, I2PD)
- Store(I2DS, Local0)
- while(LNotEqual(Local0,0x7)) {
- Store(I2DS, Local0)
- }
- }
- Case(8) {Store(0x00, I3TD)
- Store(One, I3PD)
- Store(I3DS, Local0)
- while(LNotEqual(Local0,0x7)) {
- Store(I3DS, Local0)
- }
- }
- Case(11) {
- Store(0x00, U0TD)
- Store(One, U0PD)
- Store(U0DS, Local0)
- while(LNotEqual(Local0,0x7)) {
- Store(U0DS, Local0)
- }
- }
- Case(12) {
- Store(0x00, U1TD)
- Store(One, U1PD)
- Store(U1DS, Local0)
- while(LNotEqual(Local0,0x7)) {
- Store(U1DS, Local0)
- }
- }
- Case(16) {
- Store(0x00, U2TD)
- Store(One, U2PD)
- Store(U2DS, Local0)
- while(LNotEqual(Local0,0x7)) {
- Store(U2DS, Local0)
- }
- }
- Case(26) {
- Store(0x00, U3TD)
- Store(One, U3PD)
- Store(U3DS, Local0)
- while(LNotEqual(Local0,0x7)) {
- Store(U3DS, Local0)
- }
- }
- }
- } else {
- /* put device into D3cold */
- Switch(ToInteger(Arg0))
- {
- Case(5) {
- Store(Zero, I0PD)
- Store(I0DS, Local0)
- while(LNotEqual(Local0,0x0)) {
- Store(I0DS, Local0)
- }
- Store(0x03, I0TD)
- }
- Case(6) {
- Store(Zero, I1PD)
- Store(I1DS, Local0)
- while(LNotEqual(Local0,0x0)) {
- Store(I1DS, Local0)
- }
- Store(0x03, I1TD)
- }
- Case(7) {
- Store(Zero, I2PD)
- Store(I2DS, Local0)
- while(LNotEqual(Local0,0x0)) {
- Store(I2DS, Local0)
- }
- Store(0x03, I2TD)}
- Case(8) {
- Store(Zero, I3PD)
- Store(I3DS, Local0)
- while(LNotEqual(Local0,0x0)) {
- Store(I3DS, Local0)
- }
- Store(0x03, I3TD)
- }
- Case(11) {
- Store(Zero, U0PD)
- Store(U0DS, Local0)
- while(LNotEqual(Local0,0x0)) {
- Store(U0DS, Local0)
- }
- Store(0x03, U0TD)
- }
- Case(12) {
- Store(Zero, U1PD)
- Store(U1DS, Local0)
- while(LNotEqual(Local0,0x0)) {
- Store(U1DS, Local0)
- }
- Store(0x03, U1TD)
- }
- Case(16) {
- Store(Zero, U2PD)
- Store(U2DS, Local0)
- while(LNotEqual(Local0,0x0)) {
- Store(U2DS, Local0)
- }
- Store(0x03, U2TD)
- }
- Case(26) {
- Store(Zero, U3PD)
- Store(U3DS, Local0)
- while(LNotEqual(Local0,0x0)) {
- Store(U3DS, Local0)
- }
- Store(0x03, U3TD)
- }
- }
- if(LEqual(I1TD, 3)) {
- if(LEqual(I2TD, 3)) {
- if(LEqual(I3TD, 3)) {
- if(LEqual(U0TD, 3)) {
- if(LEqual(U1TD, 3)) {
- Store(Zero, PG2_)
- }
- }
- }
- }
- }
- }
- Release(FDAS)
-}
-
-Method(FPTS,0, Serialized) /* FCH _PTS */
-{
-}
-
-Method(FWAK,0, Serialized) /* FCH _WAK */
-{
- if(LEqual(\UT0E, zero)) {
- if(LNotEqual(U0TD, 0x03)) {
- FDDC(11, 3)
- }
- }
- if(LEqual(\UT1E, zero)) {
- if(LNotEqual(U1TD, 0x03)) {
- FDDC(12, 3)
- }
- }
- if(LEqual(\IC2E, zero)) {
- if(LNotEqual(I2TD, 0x03)) {
- FDDC(7, 3)
- }
- }
- if(LEqual(\IC3E, zero)) {
- if(LNotEqual(I3TD, 0x03)) {
- FDDC(8, 3)
- }
- }
-}
-
-/*
- * Helper for setting a bit in AOACxA0 PwrGood Control
- * Arg0: bit to set or clear
- * Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0]
- */
-Method(PWGC,2, Serialized)
-{
- And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */
- if(Arg1) {
- Or(Arg0, Local0, Local0)
- } else {
- Not(Arg0, Local1)
- And(Local1, Local0, Local0)
- }
- Store(Local0, PGA3)
- if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */
- Store(PGA3, Local0)
- And(Arg0, Local0, Local0)
- while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */
- Store(PGA3, Local0)
- And(Arg0, Local0, Local0)
- }
- }
-}
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index 30224fc..5960ab3 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -13,19 +13,11 @@
* GNU General Public License for more details.
*/
-Device(PCI0) {
- /* Describe the AMD Northbridge */
- #include "northbridge.asl"
-
- /* Describe the AMD Fusion Controller Hub */
- #include "sb_pci0_fch.asl"
-}
+/* PCIe Devices, Methods, Named Objects, more */
+#include "pci0.asl"
/* Describe PCI INT[A-H] for the Southbridge */
#include "pci_int.asl"
-/* Describe the devices in the Southbridge */
-#include <sb_fch.asl>
-
-/* Add GPIO library */
-#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+/* Non-PCIe Devices */
+#include "fch.asl"
diff --git a/src/soc/amd/picasso/acpi/usb.asl b/src/soc/amd/picasso/acpi/usb.asl
deleted file mode 100644
index 2af0c1a..0000000
--- a/src/soc/amd/picasso/acpi/usb.asl
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* 0:12.0 - EHCI */
-Device(EHC0) {
- Name(_ADR, 0x00120000)
- Name(_PRW, Package() { 0xb, 3 })
- Device (RHUB) {
- Name (_ADR, Zero)
- Device (HS01) { Name (_ADR, 1) }
- Device (HS02) { Name (_ADR, 2) }
- Device (HS03) { Name (_ADR, 3) }
- Device (HS04) { Name (_ADR, 4) }
- Device (HS05) { Name (_ADR, 5) }
- Device (HS06) { Name (_ADR, 6) }
- Device (HS07) { Name (_ADR, 7) }
- Device (HS08) { Name (_ADR, 8) }
- }
-
- Method(_S0W,0) {
- Return(0)
- }
-
- Method(_S3W,0) {
- Return(4)
- }
-
- Method(_S4W,0) {
- Return(4)
- }
-} /* end EHC0 */
-
-
-/* 0:10.0 - XHCI 0*/
-Device(XHC0) {
- Name(_ADR, 0x00100000)
- Name(_PRW, Package() { 0xb, 3 })
- Device (SS01) { Name (_ADR, 1) }
- Device (SS02) { Name (_ADR, 2) }
- Device (SS03) { Name (_ADR, 3) }
-
- Method(_S0W,0) {
- Return(0)
- }
-
- Method(_S3W,0) {
- Return(4)
- }
-
- Method(_S4W,0) {
- Return(4)
- }
-
-} /* end XHC0 */
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 91bc879..8c6c1e2 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -51,12 +51,25 @@
case 0:
/* Root Hub */
return "RHUB";
+ case 2:
+ /* USB2 ports */
+ switch (dev->path.usb.port_id) {
+ case 0: return "HS01";
+ case 1: return "HS02";
+ case 2: return "HS03";
+ case 3: return "HS04";
+ case 4: return "HS05";
+ case 5: return "HS06";
+ }
+ break;
case 3:
/* USB3 ports */
switch (dev->path.usb.port_id) {
case 0: return "SS01";
case 1: return "SS02";
case 2: return "SS03";
+ case 3: return "SS04";
+ case 4: return "SS05";
}
break;
}
@@ -67,30 +80,45 @@
return NULL;
switch (dev->path.pci.devfn) {
- case GFX_DEVFN:
+ case GNB_DEVID: // GNB Root Complex
+ return "GNB";
+ case IOMMU_DEVID: // IOMMU
+ return "IOMM";
+ case GFX_DEVFN: // Internal Graphics
return "IGFX";
- case PCIE0_DEVFN:
+ /* PCIe GPP Bridges PCIE_GPP_#_DEVFN*/
+ case PCIE_GPP_0_DEVFN:
+ return "PBR0";
+ case PCIE_GPP_1_DEVFN:
+ return "PBR1";
+ case PCIE_GPP_2_DEVFN:
+ return "PBR2";
+ case PCIE_GPP_3_DEVFN:
+ return "PBR3";
+ case PCIE_GPP_4_DEVFN:
return "PBR4";
- case PCIE1_DEVFN:
+ case PCIE_GPP_5_DEVFN:
return "PBR5";
- case PCIE2_DEVFN:
+ case PCIE_GPP_6_DEVFN:
return "PBR6";
- case PCIE3_DEVFN:
- return "PBR7";
- case PCIE4_DEVFN:
- return "PBR8";
- case HDA1_DEVFN:
+ case PCIE_A_DEVFN:
+ return "PBRA";
+ case PCIE_B_DEVFN:
+ return "PBRB";
+ case HDA1_DEVFN: // HD Audio
return "AZHD";
- case LPC_DEVFN:
+ case LPC_DEVFN: // LPC Bus
return "LPCB";
- case SATA_DEVFN:
+ case SATA_DEVFN: // Sata
return "STCR";
- case SMBUS_DEVFN:
+ case SMBUS_DEVFN: // SMBUS
return "SBUS";
- case XHCI0_DEVFN:
+ case XHCI0_DEVFN: // xHCI Controller 1
return "XHC0";
- case XHCI1_DEVFN:
+ case XHCI1_DEVFN: // xHCI Controller 2
return "XHC1";
+ case DF_F0_DEVFN:
+ return "DFBS"; // Data Fabric Bus
default:
return NULL;
}
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
index 2d489ce..c7ac19b 100644
--- a/src/soc/amd/picasso/include/soc/pci_devs.h
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -45,46 +45,46 @@
#define PCIE_DEV 0x1
#define PCIE_BRIDGE_DEVID 0x15d3
-#define PCIE0_FUNC 1
-#define PCIE0_DEVFN PCI_DEVFN(PCIE_DEV, PCIE0_FUNC)
-#define SOC_PCIE0_DEV _SOC_DEV(PCIE_DEV, PCIE0_FUNC)
+#define PCIE_GPP_0_FUNC 1
+#define PCIE_GPP_0_DEVFN PCI_DEVFN(PCIE_DEV, PCIE_GPP_0_FUNC)
+#define SOC_GPP_0_DEV _SOC_DEV(PCIE_DEV, PCIE_GPP_0_FUNC)
-#define PCIE1_FUNC 2
-#define PCIE1_DEVFN PCI_DEVFN(PCIE_DEV, PCIE1_FUNC)
-#define SOC_PCIE1_DEV _SOC_DEV(PCIE_DEV, PCIE1_FUNC)
+#define PCIE_GPP_1_FUNC 2
+#define PCIE_GPP_1_DEVFN PCI_DEVFN(PCIE_DEV, PCIE_GPP_1_FUNC)
+#define SOC_GPP_1_DEV _SOC_DEV(PCIE_DEV, PCIE_GPP_1_FUNC)
-#define PCIE2_FUNC 3
-#define PCIE2_DEVFN PCI_DEVFN(PCIE_DEV, PCIE2_FUNC)
-#define SOC_PCIE2_DEV _SOC_DEV(PCIE_DEV, PCIE2_FUNC)
+#define PCIE_GPP_2_FUNC 3
+#define PCIE_GPP_2_DEVFN PCI_DEVFN(PCIE_DEV, PCIE_GPP_2_FUNC)
+#define SOC_GPP_2_DEV _SOC_DEV(PCIE_DEV, PCIE_GPP_2_FUNC)
-#define PCIE3_FUNC 4
-#define PCIE3_DEVFN PCI_DEVFN(PCIE_DEV, PCIE3_FUNC)
-#define SOC_PCIE3_DEV _SOC_DEV(PCIE_DEV, PCIE3_FUNC)
+#define PCIE_GPP_3_FUNC 4
+#define PCIE_GPP_3_DEVFN PCI_DEVFN(PCIE_DEV, PCIE_GPP_3_FUNC)
+#define SOC_GPP_3_DEV _SOC_DEV(PCIE_DEV, PCIE_GPP_3_FUNC)
-#define PCIE4_FUNC 5
-#define PCIE4_DEVFN PCI_DEVFN(PCIE_DEV, PCIE4_FUNC)
-#define SOC_PCIE4_DEV _SOC_DEV(PCIE_DEV, PCIE4_FUNC)
+#define PCIE_GPP_4_FUNC 5
+#define PCIE_GPP_4_DEVFN PCI_DEVFN(PCIE_DEV, PCIE_GPP_4_FUNC)
+#define SOC_GPP_4_DEV _SOC_DEV(PCIE_DEV, PCIE_GPP_4_FUNC)
-#define PCIE5_FUNC 6
-#define PCIE5_DEVFN PCI_DEVFN(PCIE_DEV, PCIE5_FUNC)
-#define SOC_PCIE5_DEV _SOC_DEV(PCIE_DEV, PCIE5_FUNC)
+#define PCIE_GPP_5_FUNC 6
+#define PCIE_GPP_5_DEVFN PCI_DEVFN(PCIE_DEV, PCIE_GPP_5_FUNC)
+#define SOC_GPP_5_DEV _SOC_DEV(PCIE_DEV, PCIE_GPP_5_FUNC)
-#define PCIE6_FUNC 7
-#define PCIE6_DEVFN PCI_DEVFN(PCIE_DEV, PCIE6_FUNC)
-#define SOC_PCIE6_DEV _SOC_DEV(PCIE_DEV, PCIE6_FUNC)
+#define PCIE_GPP_6_FUNC 7
+#define PCIE_GPP_6_DEVFN PCI_DEVFN(PCIE_DEV, PCIE_GPP_6_FUNC)
+#define SOC_GPP_6_DEV _SOC_DEV(PCIE_DEV, PCIE_GPP_6_FUNC)
/* Bridges 7 - 8 are to Bus A and Bus B devices*/
#define PCIE_AB_BRIDGE_DEV 0x8
#define PCIE_A_BRIDGE_DEVID 0x15db
-#define PCIE7_FUNC 1
-#define PCIE7_DEVFN PCI_DEVFN(PCIE_AB_BRIDGE_DEV, PCIE7_FUNC)
-#define SOC_PCIE7_DEV _SOC_DEV(PCIE_AB_BRIDGE_DEV, PCIE7_FUNC)
+#define PCIE_GPP_A_FUNC 1
+#define PCIE_A_DEVFN PCI_DEVFN(PCIE_AB_BRIDGE_DEV, PCIE_GPP_A_FUNC)
+#define SOC_PCIEA_DEV _SOC_DEV(PCIE_AB_BRIDGE_DEV, PCIE_GPP_A_FUNC)
#define PCIE_B_BRIDGE_DEVID 0x15dc
-#define PCIE8_FUNC 2
-#define PCIE8_DEVFN PCI_DEVFN(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC)
-#define SOC_PCIE8_DEV _SOC_DEV(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC)
+#define PCIE_GPP_B_FUNC 2
+#define PCIE_B_DEVFN PCI_DEVFN(PCIE_AB_BRIDGE_DEV, PCIE_GPP_B_FUNC)
+#define SOC_PCIEB_DEV _SOC_DEV(PCIE_AB_BRIDGE_DEV, PCIE_GPP_B_FUNC)
/* Data Fabric functions */
@@ -121,14 +121,15 @@
/* USB 3.1 */
#define XHCI0_DEV 0x0
#define XHCI0_FUNC 3
-#define XHCI0_DEVID 0x15e0
+#define XHCI0_PICASSO_DEVID 0x15e0 // Not actually used anywhere
+#define XHCI0_DALI_DEVID 0x15e5
#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC)
#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC)
/* USB 3.1 */
#define XHCI1_DEV 0x0
#define XHCI1_FUNC 4
-#define XHCI1_DEVID 0x15e1
+#define XHCI1_PICASSO_DEVID 0x15e1
#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC)
#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC)
@@ -159,23 +160,23 @@
#define SDHCI_DEVFN PCI_DEVFN(0x14, 6)
/* Internal Graphics */
-#define GFX_DEV 0x1
+#define GFX_DEV 0x0
#define GFX_FUNC 0
#define GFX_DEVID 0x15d8
#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)
#define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC)
-/* HD Audio 0 */
-#define HDA0_DEV 0x1
-#define HDA0_FUNC 1
-#define HDA0_DEVID 0x15b3
+/* Audio 0 */
+#define HDA0_DEV 0x0
+#define HDA0_FUNC 5
+#define HDA0_DEVID 0x15e2
#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
#define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC)
/* HD Audio 1 */
-#define HDA1_DEV 0x9
-#define HDA1_FUNC 2
-#define HDA1_DEVID 0x157a
+#define HDA1_DEV 0x0
+#define HDA1_FUNC 6
+#define HDA1_DEVID 0x15e3
#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC)
