| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2017 Intel Corporation. |
| ## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com> |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| chip soc/intel/skylake |
| |
| register "deep_s3_enable_ac" = "0" |
| register "deep_s3_enable_dc" = "0" |
| register "deep_s5_enable_ac" = "0" |
| register "deep_s5_enable_dc" = "0" |
| register "deep_sx_config" = "DSX_EN_WAKE_PIN" |
| |
| register "eist_enable" = "1" |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| register "gpe0_dw0" = "GPP_B" |
| register "gpe0_dw1" = "GPP_D" |
| register "gpe0_dw2" = "GPP_E" |
| |
| # Set @0x280-0x2ff I/O Range for SuperIO HWM |
| register "gen1_dec" = "0x007c0281" |
| |
| # Enable "Intel Speed Shift Technology" |
| register "speed_shift_enable" = "1" |
| |
| # Enable DPTF |
| register "dptf_enable" = "1" |
| |
| # FSP Configuration |
| register "SmbusEnable" = "1" |
| register "ScsEmmcEnabled" = "0" |
| register "ScsEmmcHs400Enabled" = "0" |
| register "ScsSdCardEnabled" = "0" |
| register "HeciEnabled" = "0" |
| register "SkipExtGfxScan" = "0" |
| register "PrimaryDisplay" = "Display_PEG" |
| register "Device4Enable" = "1" |
| register "SaGv" = "SaGv_Enabled" |
| register "PmTimerDisabled" = "0" |
| register "EnableAzalia" = "1" |
| register "DspEnable" = "0" |
| register "PchHdaVcType" = "Vc1" |
| |
| register "pirqa_routing" = "PCH_IRQ11" |
| register "pirqb_routing" = "PCH_IRQ10" |
| register "pirqc_routing" = "PCH_IRQ11" |
| register "pirqd_routing" = "PCH_IRQ11" |
| register "pirqe_routing" = "PCH_IRQ11" |
| register "pirqf_routing" = "PCH_IRQ11" |
| register "pirqg_routing" = "PCH_IRQ11" |
| register "pirqh_routing" = "PCH_IRQ11" |
| |
| # Set LPC Serial IRQ mode |
| register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| |
| # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| register "PmConfigSlpS3MinAssert" = "0x02" |
| |
| # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| register "PmConfigSlpS4MinAssert" = "0x04" |
| |
| # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| register "PmConfigSlpSusMinAssert" = "0x03" |
| |
| # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| register "PmConfigSlpAMinAssert" = "0x03" |
| |
| # VR Settings Configuration |
| #+----------------+-------+-------+-------------+-------+ |
| #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| #+----------------+-------+-------+-------------+-------+ |
| #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| #| Psi3Enable | 1 | 1 | 1 | 1 | |
| #| Psi4Enable | 1 | 1 | 1 | 1 | |
| #| ImonSlope | 0 | 0 | 0 | 0 | |
| #| ImonOffset | 0 | 0 | 0 | 0 | |
| #| IccMax* | 0 | 0 | 0 | 0 | |
| #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| #+----------------+-------+-------+-------------+-------+ |
| # * - is set automatically in the vr_config.c |
| register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| .vr_config_enable = 1, \ |
| .psi1threshold = VR_CFG_AMP(20), \ |
| .psi2threshold = VR_CFG_AMP(4), \ |
| .psi3threshold = VR_CFG_AMP(1), \ |
| .psi3enable = 1, \ |
| .psi4enable = 1, \ |
| .imon_slope = 0x0, \ |
| .imon_offset = 0x0, \ |
| .icc_max = 0x0, \ |
| .voltage_limit = 1520 \ |
| }" |
| |
| register "domain_vr_config[VR_IA_CORE]" = "{ |
| .vr_config_enable = 1, \ |
| .psi1threshold = VR_CFG_AMP(20), \ |
| .psi2threshold = VR_CFG_AMP(5), \ |
| .psi3threshold = VR_CFG_AMP(1), \ |
| .psi3enable = 1, \ |
| .psi4enable = 1, \ |
| .imon_slope = 0x0, \ |
| .imon_offset = 0x0, \ |
| .icc_max = 0x0, \ |
| .voltage_limit = 1520 \ |
| }" |
| |
| register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| .vr_config_enable = 1, \ |
| .psi1threshold = VR_CFG_AMP(20), \ |
| .psi2threshold = VR_CFG_AMP(5), \ |
| .psi3threshold = VR_CFG_AMP(1), \ |
| .psi3enable = 1, \ |
| .psi4enable = 1, \ |
| .imon_slope = 0x0, \ |
| .imon_offset = 0x0, \ |
| .icc_max = 0x0 ,\ |
| .voltage_limit = 1520 \ |
| }" |
| |
| register "domain_vr_config[VR_GT_SLICED]" = "{ |
| .vr_config_enable = 1, \ |
| .psi1threshold = VR_CFG_AMP(20), \ |
| .psi2threshold = VR_CFG_AMP(5), \ |
| .psi3threshold = VR_CFG_AMP(1), \ |
| .psi3enable = 1, \ |
| .psi4enable = 1, \ |
| .imon_slope = 0x0, \ |
| .imon_offset = 0x0, \ |
| .icc_max = 0x0, \ |
| .voltage_limit = 1520 \ |
| }" |
| |
| register "EnableLan" = "0" |
| register "PmTimerDisabled" = "0" |
| |
| # USB |
| register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" |
| register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" |
| register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" |
| register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" |
| register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" |
| register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" |
| register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" |
| register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" |
| register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" |
| register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" |
| register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" |
| register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" |
| register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" |
| |
| # SATA |
| register "EnableSata" = "1" |
| register "SataSalpSupport" = "1" |
| # SATA4 and SATA5 are located in the lower right corner of the board, |
| # but they are not populated. This is because the same PCB is used to |
| # make boards with better PCHs, which can have up to six SATA ports. |
| # However, the H110 PCH only has four SATA ports, which explains why |
| # two connectors are missing. |
| register "SataPortsEnable" = "{ \ |
| [0] = 1, \ |
| [1] = 1, \ |
| [2] = 1, \ |
| [3] = 1, \ |
| [4] = 0, \ |
| [5] = 0, \ |
| [6] = 0, \ |
| [7] = 0, \ |
| }" |
| |
| # PCH UART, SPI, I2C |
| register "SerialIoDevMode" = "{ \ |
| [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ |
| [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ |
| }" |
| |
| # Set params for PEG 0:1:0 |
| register "Peg0MaxLinkWidth" = "Peg0_x16" |
| # Configure PCIe clockgen in PCH |
| # PEG0 uses SRCCLKREQ0 and CLKSRC0 |
| register "PcieRpClkReqSupport[0]" = "1" |
| register "PcieRpClkReqNumber[0]" = "0" |
| register "PcieRpClkSrcNumber[0]" = "0" |
| |
| # Enable Root port 6(x1) for LAN. |
| register "PcieRpEnable[5]" = "1" |
| # Disable CLKREQ#, since onboard LAN is always present |
| register "PcieRpClkReqSupport[5]" = "0" |
| # Enable Advanced Error Reporting |
| register "PcieRpAdvancedErrorReporting[5]" = "1" |
| # Enable Latency Tolerance Reporting Mechanism |
| register "PcieRpLtrEnable[5]" = "1" |
| # Use CLK SRC 1 |
| register "PcieRpClkSrcNumber[5]" = "1" |
| |
| # Enable Root port 5 (x1) for PCIE slot. |
| register "PcieRpEnable[4]" = "1" |
| # Enable CLKREQ# |
| register "PcieRpClkReqSupport[4]" = "1" |
| # Use SRCCLKREQ2# |
| register "PcieRpClkReqNumber[4]" = "2" |
| # Enable Advanced Error Reporting |
| register "PcieRpAdvancedErrorReporting[4]" = "1" |
| # Enable Latency Tolerance Reporting Mechanism |
| register "PcieRpLtrEnable[4]" = "1" |
| # Use CLK SRC 2 |
| register "PcieRpClkSrcNumber[4]" = "2" |
| # Use Hot Plug subsystem |
| register "PcieRpHotPlug[4]" = "1" |
| |
| # Enable Root port 7(x1) for PCIE slot. |
| register "PcieRpEnable[6]" = "1" |
| # Enable CLKREQ# |
| register "PcieRpClkReqSupport[6]" = "1" |
| # Use SRCCLKREQ3# |
| register "PcieRpClkReqNumber[6]" = "3" |
| # Enable Advanced Error Reporting |
| register "PcieRpAdvancedErrorReporting[6]" = "1" |
| # Enable Latency Tolerance Reporting Mechanism |
| register "PcieRpLtrEnable[6]" = "1" |
| # Use CLK SRC 3 |
| register "PcieRpClkSrcNumber[6]" = "3" |
| # Use Hot Plug subsystem |
| register "PcieRpHotPlug[6]" = "1" |
| |
| # PL2 override 91W |
| register "tdp_pl2_override" = "91" |
| |
| # Send an extra VR mailbox command for the PS4 exit issue |
| register "SendVrMbxCmd" = "2" |
| |
| device cpu_cluster 0 on |
| device lapic 0 on end |
| end |
| device domain 0 on |
| device pci 00.0 on # Host Bridge |
| subsystemid 0x1849 0x191f |
| end |
| device pci 01.0 on # PEG |
| subsystemid 0x1849 0x1901 |
| end |
| device pci 02.0 on # Integrated Graphics Device |
| subsystemid 0x1849 0x1912 |
| end |
| device pci 04.0 on end # Thermal Subsystem |
| device pci 08.0 off end # Gaussian Mixture Model |
| device pci 14.0 on # USB xHCI |
| subsystemid 0x1849 0xa131 |
| end |
| device pci 14.1 off end # USB xDCI (OTG) |
| device pci 14.2 on # Thermal Subsystem |
| subsystemid 0x1849 0xa131 |
| end |
| device pci 15.0 off end # I2C #0 |
| device pci 15.1 off end # I2C #1 |
| device pci 15.2 off end # I2C #2 |
| device pci 15.3 off end # I2C #3 |
| device pci 16.0 on # Management Engine Interface 1 |
| subsystemid 0x1849 0xa131 |
| end |
| device pci 16.1 off end # Management Engine Interface 2 |
| device pci 16.2 off end # Management Engine IDE-R |
| device pci 16.3 off end # Management Engine KT Redirection |
| device pci 16.4 off end # Management Engine Interface 3 |
| device pci 17.0 on # SATA |
| subsystemid 0x1849 0xa102 |
| end |
| device pci 19.0 off end # UART #2 |
| device pci 19.1 off end # I2C #5 |
| device pci 19.2 off end # I2C #4 |
| device pci 1c.0 on end # PCI Express Port 1 |
| device pci 1c.1 off end # PCI Express Port 2 |
| device pci 1c.2 off end # PCI Express Port 3 |
| device pci 1c.3 off end # PCI Express Port 4 |
| device pci 1c.4 on end # PCI Express Port 5 |
| device pci 1c.5 on end # PCI Express Port 6 |
| device pci 1c.6 on end # PCI Express Port 7 |
| device pci 1c.7 off end # PCI Express Port 8 |
| device pci 1d.0 off end # PCI Express Port 9 |
| device pci 1d.1 off end # PCI Express Port 10 |
| device pci 1d.2 off end # PCI Express Port 11 |
| device pci 1d.3 off end # PCI Express Port 12 |
| device pci 1e.0 off end # UART #0 |
| device pci 1e.1 off end # UART #1 |
| device pci 1e.2 off end # GSPI #0 |
| device pci 1e.3 off end # GSPI #1 |
| device pci 1e.4 off end # eMMC |
| device pci 1e.5 off end # SDIO |
| device pci 1e.6 off end # SDCard |
| device pci 1f.0 on # LPC bridge |
| subsystemid 0x1849 0x1a43 |
| |
| chip superio/common |
| device pnp 2e.0 on # passes SIO base addr to SSDT gen |
| |
| chip superio/nuvoton/nct6791d |
| device pnp 2e.1 on |
| # Global Control Registers |
| # Device IRQ Polarity |
| irq 0x13 = 0x00 |
| irq 0x14 = 0x00 |
| # Global Option |
| irq 0x24 = 0xfb |
| irq 0x27 = 0x10 |
| # Multi Function |
| irq 0x1a = 0xb0 |
| irq 0x1b = 0xe6 |
| irq 0x2a = 0x04 |
| irq 0x2c = 0x40 |
| irq 0x2d = 0x03 |
| |
| # Parallel Port |
| io 0x60 = 0x0378 |
| irq 0x70 = 7 |
| drq 0x74 = 4 # No DMA |
| irq 0xf0 = 0x3c # Printer mode |
| end |
| device pnp 2e.2 on # UART A |
| io 0x60 = 0x03f8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.3 on # IR |
| io 0x60 = 0x02f8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.5 on # PS/2 KBC |
| io 0x60 = 0x0060 |
| io 0x62 = 0x0064 |
| irq 0x70 = 1 # Keyboard |
| irq 0x72 = 12 # Mouse |
| end |
| device pnp 2e.6 off end # CIR |
| device pnp 2e.7 on # GPIO6 |
| irq 0xf6 = 0xff |
| irq 0xf7 = 0xff |
| irq 0xf8 = 0xff |
| end |
| device pnp 2e.107 on # GPIO7 |
| irq 0xe0 = 0x7f |
| irq 0xe1 = 0x0d |
| end |
| device pnp 2e.207 on # GPIO8 |
| irq 0xe6 = 0xff |
| irq 0xe7 = 0xff |
| irq 0xed = 0xff |
| end |
| device pnp 2e.8 off end # WDT |
| device pnp 2e.108 on end # GPIO0 |
| device pnp 2e.308 off end # GPIO base |
| device pnp 2e.408 off end # WDTMEM |
| device pnp 2e.708 on end # GPIO1 |
| device pnp 2e.9 on end # GPIO2 |
| device pnp 2e.109 on # GPIO3 |
| irq 0xe4 = 0x7b |
| irq 0xe5 = 0x02 |
| irq 0xea = 0x04 |
| end |
| device pnp 2e.209 on # GPIO4 |
| irq 0xf0 = 0x7f |
| irq 0xf1 = 0x80 |
| end |
| device pnp 2e.309 on # GPIO5 |
| irq 0xf4 = 0xdf |
| irq 0xf5 = 0xd5 |
| end |
| device pnp 2e.a on |
| # Power RAM in S3 and let the PCH |
| # handle power failure actions |
| irq 0xe4 = 0x70 |
| # Set HWM reset source to LRESET# |
| irq 0xe7 = 0x01 |
| end # ACPI |
| device pnp 2e.b on # HWM, LED |
| io 0x60 = 0x0290 |
| io 0x62 = 0 |
| irq 0x70 = 0 |
| end |
| device pnp 2e.d off end # BCLK, WDT2, WDT_MEM |
| device pnp 2e.e off end # CIR wake-up |
| device pnp 2e.f off end # GPIO PP/OD |
| device pnp 2e.14 off end # SVID, Port 80 UART |
| device pnp 2e.16 off end # DS5 |
| device pnp 2e.116 off end # DS3 |
| device pnp 2e.316 on end # PCHDSW |
| device pnp 2e.416 off end # DSWWOPT |
| device pnp 2e.516 on end # DS3OPT |
| device pnp 2e.616 on end # DSDSS |
| device pnp 2e.716 off end # DSPU |
| end # chip superio/nuvoton/nct6791d |
| |
| end # device pnp 2e.0 |
| end # chip superio/common |
| |
| chip drivers/pc80/tpm |
| device pnp 4e.0 on end # TPM module |
| end |
| end # LPC Interface |
| device pci 1f.1 on end # P2SB |
| device pci 1f.2 on end # Power Management Controller |
| device pci 1f.3 on end # Intel HDA |
| device pci 1f.4 on end # SMBus |
| device pci 1f.5 on end # PCH SPI |
| device pci 1f.6 off end # GbE |
| end |
| end |
