| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config NORTHBRIDGE_INTEL_I440BX |
| bool |
| select NO_MMCONF_SUPPORT |
| select HAVE_DEBUG_RAM_SETUP |
| select UDELAY_IO |
| |
| config SDRAMPWR_4DIMM |
| bool |
| depends on NORTHBRIDGE_INTEL_I440BX |
| default n |
| help |
| This option affects how the SDRAMC register is programmed. |
| Memory clock signals will not be routed properly if this option |
| is set wrong. |
| |
| If your board has 4 DIMM slots, you must use select this option, in |
| your Kconfig file of the board. On boards with 3 DIMM slots, |
| do _not_ select this option. |
