UPSTREAM: drivers/intel/fsp2_0: Allocate cfg_region_size for UPD
In FSP-S, the driver constructs its pointer to UPD using the offset
in the header. Similarly, use the header's cfg_region_size for
allocating memory and copying the default configuration.
Add sanity checks for unexpedted configuration and UPD header
conditions.
TEST=Verify OK on Mandolin, verify a mock error condition
BUG=b:140648081
Change-Id: I1cee7da35e3b705e03caa9d519db3a5ad57fa945
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 71dbcf127ad26b6caa68e242f1404aae27bb49ae
Original-Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/35349
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1801644
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index e72e4ac..ecc6e96 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -39,9 +39,17 @@
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Invalid FSPS signature\n");
- upd = xmalloc(sizeof(FSPS_UPD));
+ /* Disallow invalid config regions. Default settings are likely bad
+ * choices for coreboot, and different sized UPD from what the region
+ * allows is potentially a build problem.
+ */
+ if (!hdr->cfg_region_size || hdr->cfg_region_size != sizeof(FSPS_UPD))
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "Invalid FSPS UPD region\n");
- memcpy(upd, supd, sizeof(FSPS_UPD));
+ upd = xmalloc(hdr->cfg_region_size);
+
+ memcpy(upd, supd, hdr->cfg_region_size);
/* Give SoC/mainboard a chance to populate entries */
platform_fsp_silicon_init_params_cb(upd);
