src/mainboard/roda/rv11/variants/rv11/devicetree.cb

##
## This file is part of the coreboot project.
##
## Copyright (C) 2015-2016 secunet Security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

chip northbridge/intel/sandybridge
	# IGD Displays
	register "gfx.ndid" = "3"
	register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000100, }"

	# Enable Panel as eDP and configure power delays
	register "gpu_panel_port_select" = "1"			# eDP_A
	register "gpu_panel_power_cycle_delay" = "6"		# 500ms
	register "gpu_panel_power_up_delay" = "2000"		# 200ms
	register "gpu_panel_power_down_delay" = "500"		# 50ms
	register "gpu_panel_power_backlight_on_delay" = "1"	# 100us as recommended by PRM
	register "gpu_panel_power_backlight_off_delay" = "2000"	# 200ms

	# Set backlight PWM values for eDP
	register "gpu_cpu_backlight" = "0x0000001a"
	register "gpu_pch_backlight" = "0x002e0000"

	device cpu_cluster 0 on
		chip cpu/intel/socket_rPGA989
			device lapic 0 on end
		end
		chip cpu/intel/model_206ax
			# Magic APIC ID to locate this chip
			device lapic 0xacac off end

			register "c1_acpower" = "1"	# ACPI(C1) = MWAIT(C1)
			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
			register "c3_acpower" = "0"

			register "c1_battery" = "1"	# ACPI(C1) = MWAIT(C1)
			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
			register "c3_battery" = "0"
		end
	end

	device domain 0 on
		device pci 00.0 on end # host bridge
		device pci 02.0 on end # vga controller

		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
			# Enable both SATA ports 0, 1
			register "sata_port_map" = "0x03"
			# Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
			register "sata_interface_speed_support" = "0x3"

			# Route GPI7 (EC SCI) as SCI
			register "gpi7_routing" = "2"

			# Enable GPE17 (GPI7) and TCO SCI
			register "gpe0_en" = "0x00800040"

			# Disable root port coalescing
			register "pcie_port_coalesce" = "0"
			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"

			register "p_cnt_throttling_supported" = "1"

			register "xhci_overcurrent_mapping"	= "0x00080401"
			register "xhci_switchable_ports"	= "0x0f"
			register "superspeed_capable_ports"	= "0x0f"

			register "spi_uvscc" = "0x2005"
			register "spi_lvscc" = "0x2005"

			device pci 14.0 on end # USB 3.0 Controller
			device pci 16.0 on end # Management Engine Interface 1
			device pci 16.1 off end # Management Engine Interface 2
			device pci 16.2 off end # Management Engine IDE-R
			device pci 16.3 off end # Management Engine KT
			device pci 19.0 on end # Intel Gigabit Ethernet
			device pci 1a.0 on end # USB2 EHCI #2
			device pci 1b.0 on # High Definition Audio
				subsystemid 0x1a86 0x4352
			end

			# Disabling 1c.0 might break IRQ settings as it enables port coalescing
			device pci 1c.0 on end # PCIe Port #1
			device pci 1c.1 on end # PCIe Port #2
			device pci 1c.2 off end # PCIe Port #3
			device pci 1c.3 on end # PCIe Port #4
			device pci 1c.4 on end # PCIe Port #5
			device pci 1c.5 off end # PCIe Port #6
			device pci 1c.6 on end # PCIe Port #7
			device pci 1c.7 on end # PCIe Port #8

			device pci 1d.0 on end # USB2 EHCI #1
			device pci 1e.0 off end # PCI bridge
			device pci 1f.0 on # LPC bridge
				chip ec/roda/it8518
					# 60h/64h KBC
					device pnp ff.0 on # dummy address
					end
				end
			end # LPC bridge
			device pci 1f.2 on end # SATA Controller 1
			device pci 1f.3 on end # SMBus
			device pci 1f.5 off end # SATA Controller 2
			device pci 1f.6 off end # Thermal
		end
	end
end