| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2014 Google Inc. |
| * Copyright (C) 2015 Intel Corporation. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef _SOC_MSR_H_ |
| #define _SOC_MSR_H_ |
| |
| #include <intelblocks/msr.h> |
| |
| #define MSR_PIC_MSG_CONTROL 0x2e |
| #define MSR_EMULATE_PM_TIMER 0x121 |
| #define EMULATE_PM_TMR_EN (1 << 16) |
| #define EMULATE_DELAY_OFFSET_VALUE 20 |
| #define EMULATE_DELAY_VALUE 0x13 |
| #define MSR_LT_LOCK_MEMORY 0x2e7 |
| #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 |
| #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 |
| #define MSR_VR_CURRENT_CONFIG 0x601 |
| #define MSR_VR_MISC_CONFIG 0x603 |
| #define MSR_PL3_CONTROL 0x615 |
| #define MSR_VR_MISC_CONFIG2 0x636 |
| #define MSR_PP0_POWER_LIMIT 0x638 |
| #define MSR_PP1_POWER_LIMIT 0x640 |
| #define MSR_PLATFORM_POWER_LIMIT 0x65c |
| |
| #endif |
