| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2007-2010 coresystems GmbH |
| * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| * Copyright (C) 2014 Vladimir Serbinenko |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <stdint.h> |
| #include "pch.h" |
| #include <southbridge/intel/common/rcba.h> |
| #include "northbridge/intel/sandybridge/sandybridge.h" |
| |
| void |
| southbridge_configure_default_intmap(void) |
| { |
| /* |
| * GFX INTA -> PIRQA (MSI) |
| * D28IP_P1IP SLOT1 INTA -> PIRQB |
| * D28IP_P2IP SLOT2 INTB -> PIRQF |
| * D28IP_P3IP SLOT3 INTC -> PIRQD |
| * D28IP_P5IP SLOT5 INTC -> PIRQD |
| * D29IP_E1P EHCI1 INTA -> PIRQD |
| * D26IP_E2P EHCI2 INTA -> PIRQF |
| * D31IP_SIP SATA INTA -> PIRQB (MSI) |
| * D31IP_SMIP SMBUS INTB -> PIRQH |
| * D31IP_TTIP THRT INTC -> PIRQA |
| * D27IP_ZIP HDA INTA -> PIRQA (MSI) |
| * |
| |
| */ |
| |
| RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| RCBA32(D29IP) = (INTA << D29IP_E1P); |
| RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | |
| (INTC << D28IP_P3IP) | (INTC << D28IP_P5IP); |
| RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| RCBA32(D26IP) = (INTA << D26IP_E2P); |
| RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| |
| /* Device interrupt route registers */ |
| DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); |
| DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); |
| DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); |
| DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); |
| DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| |
| /* Enable IOAPIC (generic) */ |
| RCBA16(EOIC) = 0x0100; |
| /* PCH BWG says to read back the IOAPIC enable register */ |
| (void) RCBA16(EOIC); |
| } |
| |
| void |
| southbridge_rcba_config(void) |
| { |
| RCBA32(FD) = PCH_DISABLE_ALWAYS; |
| } |