UPSTREAM: mb/google/reef/sand: Override USB2 phy settings
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need
to be overridden.
port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
BUG=b:72623892
BRANCH=master
TEST=emerge-sand coreboot chromeos-bootimage
Change-Id: Ib97e7ee1f104ba9ca2e2b1e88a9808c3185703fc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: aef0d6b0a7ec867ee29acf9e1c695be27626f239
Original-Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769
Original-Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Original-Reviewed-on: https://review.coreboot.org/23879
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/943591
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index 0735a35..a6692e6 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -112,6 +112,22 @@
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
+ # Override USB2 PER PORT register (PORT 1)
+ register "usb2eye[1]" = "{
+ .Usb20PerPortPeTxiSet = 4,
+ .Usb20PerPortTxiSet = 4,
+ .Usb20IUsbTxEmphasisEn = 1,
+ .Usb20PerPortTxPeHalf = 0,
+ }"
+
+ # Override USB2 PER PORT register (PORT 4)
+ register "usb2eye[4]" = "{
+ .Usb20PerPortPeTxiSet = 7,
+ .Usb20PerPortTxiSet = 7,
+ .Usb20IUsbTxEmphasisEn = 1,
+ .Usb20PerPortTxPeHalf = 0,
+ }"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
