blob: c3cc195af4b96eaddf837c9f4b66d3307fbf4414 [file] [log] [blame]
ifeq ($(CONFIG_SOC_EXAMPLE_MIN86),y)
bootblock-y += cache_as_ram.S
bootblock-y += ../../../cpu/intel/car/bootblock.c
postcar-y += exit_car.S
romstage-y += romstage.c
ramstage-y += chip.c
ramstage-y += timer.c
endif