| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| */ |
| |
| #include <console/console.h> |
| #include <device/device.h> |
| #include <device/pci.h> |
| #include <arch/io.h> |
| #include <cpu/x86/msr.h> |
| #include <device/pci_def.h> |
| #include <southbridge/amd/sb800/sb800.h> |
| #include <arch/acpi.h> |
| #include "BiosCallOuts.h" |
| #include <cpu/amd/agesa/s3_resume.h> |
| #include <cpu/amd/mtrr.h> |
| #include "SBPLATFORM.h" |
| |
| void set_pcie_reset(void); |
| void set_pcie_dereset(void); |
| |
| /** |
| * TODO |
| * SB CIMx callback |
| */ |
| void set_pcie_reset(void) |
| { |
| } |
| |
| /** |
| * TODO |
| * mainboard specific SB CIMx callback |
| */ |
| void set_pcie_dereset(void) |
| { |
| } |
| |
| |
| /********************************************** |
| * Enable the dedicated functions of the board. |
| **********************************************/ |
| static void mainboard_enable(device_t dev) |
| { |
| printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| |
| /* |
| * The mainboard is the first place that we get control in ramstage. Check |
| * for S3 resume and call the approriate AGESA/CIMx resume functions. |
| */ |
| #if CONFIG_HAVE_ACPI_RESUME |
| acpi_slp_type = acpi_get_sleep_type(); |
| #endif |
| |
| /* enable GPP CLK0 thru CLK1 */ |
| /* disable GPP CLK2 thru SLT_GFX_CLK */ |
| u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); |
| *(misc_mem_clk_cntrl + 0) = 0xFF; |
| *(misc_mem_clk_cntrl + 1) = 0x00; |
| *(misc_mem_clk_cntrl + 2) = 0x00; |
| *(misc_mem_clk_cntrl + 3) = 0x00; |
| *(misc_mem_clk_cntrl + 4) = 0x00; |
| |
| /* |
| * Initialize ASF registers to an arbitrary address because someone |
| * long ago set things up this way inside the SPD read code. The |
| * SPD read code has been made generic and moved out of the board |
| * directory, so the ASF init is being done here. |
| */ |
| pm_iowrite(0x29, 0x80); |
| pm_iowrite(0x28, 0x61); |
| } |
| |
| struct chip_operations mainboard_ops = { |
| .enable_dev = mainboard_enable, |
| }; |