| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2011 Google Inc. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config SOUTHBRIDGE_INTEL_BD82X6X |
| bool |
| |
| config SOUTHBRIDGE_INTEL_C216 |
| bool |
| |
| if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 |
| |
| config SOUTH_BRIDGE_OPTIONS # dummy |
| def_bool y |
| select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| select SOUTHBRIDGE_INTEL_COMMON |
| select IOAPIC |
| select HAVE_HARD_RESET |
| select HAVE_USBDEBUG_OPTIONS |
| select HAVE_SMI_HANDLER |
| select USE_WATCHDOG_ON_BOOT |
| select PCIEXP_ASPM |
| select PCIEXP_COMMON_CLOCK |
| select SPI_FLASH |
| select COMMON_FADT |
| select ACPI_SATA_GENERATOR |
| select HAVE_INTEL_FIRMWARE |
| select SOUTHBRIDGE_INTEL_COMMON_GPIO |
| select RTC |
| |
| config EHCI_BAR |
| hex |
| default 0xfef00000 |
| |
| config DRAM_RESET_GATE_GPIO |
| int |
| default 60 |
| |
| config BOOTBLOCK_SOUTHBRIDGE_INIT |
| string |
| default "southbridge/intel/bd82x6x/bootblock.c" |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default n |
| help |
| If you set this option to y, the serial IRQ machine will be |
| operated in continuous mode. |
| |
| config HPET_MIN_TICKS |
| hex |
| default 0x80 |
| |
| config HAVE_IFD_BIN |
| def_bool y |
| |
| config BUILD_WITH_FAKE_IFD |
| def_bool !HAVE_IFD_BIN |
| |
| endif |
| |
| if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK |
| |
| choice |
| prompt "Flash ROM locking on S3 resume" |
| default LOCK_SPI_ON_RESUME_NONE |
| |
| config LOCK_SPI_ON_RESUME_NONE |
| bool "Don't lock ROM sections on S3 resume" |
| |
| config LOCK_SPI_ON_RESUME_RO |
| bool "Lock all flash ROM sections on S3 resume" |
| help |
| If the flash ROM shall be protected against write accesses from the |
| operating system (OS), the locking procedure has to be repeated after |
| each resume from S3. Select this if you never want to update the flash |
| ROM from within your OS. Notice: Even with this option, the write lock |
| has still to be enabled on the normal boot path (e.g. by the payload). |
| |
| config LOCK_SPI_ON_RESUME_NO_ACCESS |
| bool "Lock and disable reads all flash ROM sections on S3 resume" |
| help |
| If the flash ROM shall be protected against all accesses from the |
| operating system (OS), the locking procedure has to be repeated after |
| each resume from S3. Select this if you never want to update the flash |
| ROM from within your OS. Notice: Even with this option, the lock |
| has still to be enabled on the normal boot path (e.g. by the payload). |
| |
| endchoice |
| |
| endif |