CHROMIUM: soc/intel/skylake: Enable the ACPI PM Timer explicitly
Explicitly enable the ACPI PM Timer if the variable PmTimerDisabled is
set to "0". This is necessary because the ACPI PM timer is enabled by
default after reset, but after silicon initialization by FSP in
src/drivers/intel/fsp2_0/silicon_init.c:50, the timer is disabled.
Since upstream coreboot does not support the Fizz platform, this patch
is denoted as a CHROMIUM patch.
BUG=b:314260167
TEST=Build and deploy the firmware onto the device. Run the system. Use
the “iotools mmio_read8 0xfe0000fc” command to read the ACPI Timer
Control (ACPI_TMR_CTL) register. Verify if the second bit is cleared to
ensure that the ACPI PM timer is enabled.
Change-Id: I4612b0c434c28485026366993552e3655b6fd08a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5182716
Commit-Queue: Marek Maślanka <mmaslanka@google.com>
Tested-by: Marek Maślanka <mmaslanka@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 25b7484..d514a54 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -125,18 +125,18 @@
*/
pch_thermal_configuration();
+ reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
/*
* Disable ACPI PM timer based on dt policy
*
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
* Disabling ACPI PM timer also switches off TCO
*/
-
- if (config->PmTimerDisabled) {
- reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
+ if (config->PmTimerDisabled)
reg8 |= (1 << 1);
- write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
- }
+ else
+ reg8 &= ~(1 << 1);
+ write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
/* Disable XTAL shutdown qualification for low power idle. */
if (config->s0ix_enable) {
