UPSTREAM: mb/google/fizz: Add USB port info
This adds all USB ports to the device tree. Additionally, it adds _PS0
and _PS3 ACPI methods for the visible USB A ports, which makes it
possible to control the port power (VBUS) of each port individually.
BUG=b:78140956
BRANCH=none
TEST=Run `cat /sys/firmware/acpi/tables/DSDT > dsdt.aml` and then
`iasl dsdt.aml` and verify that _UPC, _PLD, _PS0 and _PS3 methods
exists for all USB ports in dsdt.dsl.
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2ad7ea07b82f99ce9ff751774143e6ebbf02090c
Original-Change-Id: I80ba090f323fbf9fc2b333b1c647b7dfb3393ff6
Original-Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/26472
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1084695
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
(cherry picked from commit 9b61377b2e2d42e2d897d423f01f3351216d1972)
Had to manually add _UPC and _PLD methods for all USB ports since this
branch cannot generate them from the device tree.
Change-Id: I707bbcacc006f696905afdc967221ca3ddd0a6a5
Signed-off-by: Emil Lundmark <lndmrk@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096937
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 2f3b4cfd12607af1f0e1a6d8a7ef25bc4b8d4263)
Reviewed-on: https://chromium-review.googlesource.com/1112520
Reviewed-by: Shelley Chen <shchen@chromium.org>
Commit-Queue: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 1ca3090..dd0be0c 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -6,6 +6,7 @@
select DRIVERS_I2C_GENERIC
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_LPC
select HAVE_ACPI_RESUME
diff --git a/src/mainboard/google/fizz/acpi/usb.asl b/src/mainboard/google/fizz/acpi/usb.asl
new file mode 100644
index 0000000..4cbf168
--- /dev/null
+++ b/src/mainboard/google/fizz/acpi/usb.asl
@@ -0,0 +1,261 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.XHCI.RHUB.HS02)
+{
+ /* USB-A Rear Right Port USB 2.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ Zero, /* USB Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* Visible */
+ Method (_PLD, 0, NotSerialized)
+ {
+ Return (GPLD (One))
+ }
+ /* D0 state - VBUS is on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (2)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (2)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS03)
+{
+ /* USB-A Front Right Port USB 2.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ Zero, /* USB Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* Visible */
+ Method (_PLD, 0, NotSerialized)
+ {
+ Return (GPLD (One))
+ }
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (3)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (3)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS04)
+{
+ /* USB-A Front Left Port USB 2.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ Zero, /* USB Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* Visible */
+ Method (_PLD, 0, NotSerialized)
+ {
+ Return (GPLD (One))
+ }
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (4)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (4)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS05)
+{
+ /* USB-A Rear Left Port USB 2.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ Zero, /* USB Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* Visible */
+ Method (_PLD, 0, NotSerialized)
+ {
+ Return (GPLD (One))
+ }
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (0)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (0)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS06)
+{
+ /* USB-A Rear Middle Port USB 2.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ Zero, /* USB Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* Visible */
+ Method (_PLD, 0, NotSerialized)
+ {
+ Return (GPLD (One))
+ }
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (1)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (1)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS01)
+{
+ /* USB-C Rear Port USB 3.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ 0x03, /* USB 3.0 Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS02)
+{
+ /* USB-A Rear Right Port USB 3.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ 0x03, /* USB 3.0 Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (2)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (2)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS03)
+{
+ /* USB-A Front Right Port USB 3.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ 0x03, /* USB 3.0 Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (3)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (3)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS04)
+{
+ /* USB-A Front Left Port USB 3.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ 0x03, /* USB 3.0 Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (4)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (4)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS05)
+{
+ /* USB-A Rear Left Port USB 3.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ 0x03, /* USB 3.0 Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (0)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (0)
+ }
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS06)
+{
+ /* USB-A Rear Middle Port USB 3.0 */
+ Name (_UPC, Package (0x04)
+ {
+ 0xFF, /* Connectable */
+ 0x03, /* USB 3.0 Port */
+ Zero, /* Reserved */
+ Zero /* Reserved */
+ })
+ /* D0 state - VBUS on */
+ Method (_PS0)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPS (1)
+ }
+ /* D3 state - VBUS off */
+ Method (_PS3)
+ {
+ \_SB.PCI0.LPCB.EC0.UPPC (1)
+ }
+}
diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl
index 24abfc1..69d9158 100644
--- a/src/mainboard/google/fizz/dsdt.asl
+++ b/src/mainboard/google/fizz/dsdt.asl
@@ -67,4 +67,7 @@
/* Dynamic Platform Thermal Framework */
#include "acpi/dptf.asl"
}
+
+ /* USB port entries */
+ #include "acpi/usb.asl"
}
