UPSTREAM: soc/intel/jasperlake: Revert CdClock setting
Revert CdClock setting and use default value 0xff.
Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.
BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"
Cq-Depend: chrome-internal:4662167
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Original-Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
GitOrigin-RevId: dec327b03b2fbf6dc6f89599107f645ed6a5396f
Change-Id: Idc4316dfbdff5b29c6c8085581b19ae69c8df8af
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3613501
Tested-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: CopyBot Service Account <copybot.service@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Commit-Queue: Nick Vaccaro <nvaccaro@google.com>
Tested-by: Simon Yang <simon1.yang@intel.corp-partner.google.com>
(cherry picked from commit ef89207f749bb6cd9525242c2365c4035d9a3808)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3616196
Commit-Queue: Henry Sun <henrysun@google.com>
Tested-by: Jongpil Jung <jongpil19.jung@samsung.corp-partner.google.com>
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
index 30e5e45..7496428 100644
--- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -2,9 +2,6 @@
# MIPI display panel
register "DdiPortAConfig" = "2" # DdiPortMipiDsi
- # Core Display Clock Frequency selection
- register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
# Enable Acoustic noise mitigation and set slew rate to 1/8
# Rest of the parameters are 0 by default.
register "AcousticNoiseMitigation" = "1"
diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
index 73a5f49..fcf66f2 100644
--- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb
@@ -75,9 +75,6 @@
register "tcc_offset" = "8" # TCC of 97C
- # Core Display Clock Frequency selection
- register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
device domain 0 on
device pci 04.0 on
# Default DPTF Policy for all Dedede boards if not overridden
diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
index e0af22d..66fc4ea 100644
--- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb
@@ -108,9 +108,6 @@
register "SlowSlewRate" = "SlewRateFastBy8"
register "FastPkgCRampDisable" = "1"
- # Core Display Clock Frequency selection
- register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
index da8760b..5249231 100644
--- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb
@@ -69,9 +69,6 @@
.tdp_pl2_override = 12,
}"
- # Core Display Clock Frequency selection
- register "cd_clock" = "CD_CLOCK_172_8_MHZ"
-
device domain 0 on
device pci 04.0 on
chip drivers/intel/dptf
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 4c749d2..1d9b867 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -442,8 +442,6 @@
CD_CLOCK_312_MHZ = 5,
CD_CLOCK_552_MHZ = 6,
CD_CLOCK_556_8_MHZ = 7,
- CD_CLOCK_648_MHZ = 8,
- CD_CLOCK_652_8_MHZ = 9,
} cd_clock;
};
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
index 02d9d76..c12345f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
@@ -876,7 +876,7 @@
/** Offset 0x0436 - CdClock Frequency selection
0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, 6: 556.8 MHz,
- 7: 648 MHz, 8: 652.8 MHz, 0xff: 648 MHz (Default)
+ 0xff: 556.8 MHz (Default)
**/
UINT8 CdClock;
