| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2011 Google Inc. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| ## You should have received a copy of the GNU General Public License |
| ## along with this program; if not, write to the Free Software |
| ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| ## |
| |
| config SOUTHBRIDGE_INTEL_BD82X6X |
| bool |
| |
| config SOUTHBRIDGE_INTEL_C216 |
| bool |
| |
| if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 |
| |
| config SOUTH_BRIDGE_OPTIONS # dummy |
| def_bool y |
| select IOAPIC |
| select HAVE_HARD_RESET |
| select HAVE_USBDEBUG |
| select USE_WATCHDOG_ON_BOOT |
| select PCIEXP_ASPM |
| select PCIEXP_COMMON_CLOCK |
| select SPI_FLASH |
| |
| config EHCI_BAR |
| hex |
| default 0xfef00000 |
| |
| config EHCI_DEBUG_OFFSET |
| hex |
| default 0xa0 |
| |
| config BOOTBLOCK_SOUTHBRIDGE_INIT |
| string |
| default "southbridge/intel/bd82x6x/bootblock.c" |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default n |
| help |
| If you set this option to y, the serial IRQ machine will be |
| operated in continuous mode. |
| |
| endif |
