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cos / mirrors / cros / chromiumos / third_party / coreboot / 4b25ed2fcdca84df5ed99eb05015302a47d964c1
commit4b25ed2fcdca84df5ed99eb05015302a47d964c1[log] [tgz]
authorJonathan Zhang <jonzhang@fb.com>Mon Sep 14 16:27:13 2020 -0700
committerCommit Bot <commit-bot@chromium.org>Wed Oct 07 01:46:04 2020 +0000
tree07abfc4f1a4ac2754a31a91384974eaed3a4210e
parent5cfec4459d3ab7c5fd77beb40a43ee24406832f7 [diff]
UPSTREAM: drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region

APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record
Table) memory region:
* Bootloader (firmware) generates UEFI CPER (Common Platform Error
Record) records, and populates BERT region.
* OS parses ACPI BERT table, finds the BERT region address, inteprets
the data and processes it accordingly.

When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize,
so FSP allocates memory region for it. The APEI BERT region is placed
on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE.

Apart from APEI BERT region, we also have plan to add APEI HEST region
which holds OS runtime hardware error record, based on firmware
first hardware error handling model. HEST region will be reserved
same way as BERT region.

Note that CBMEM region can not be used for such purpose, the OS
(bert/hest) drivers are not able to access data held in CBMEM region,
as CBMEM is set as type 16 (configuration table).

An option considered was to reserve the BERT region under CBMEM.
However, we do not know the size of CBMEM till acpi tables are set up.
On the other hand, BERT region needs to be filled up before ACPI BERT
table is finalized.

BUG=none
BRANCH=none
TEST=none

Change-Id: I331b45b540b9e7cd8be634935dbc7bfa86405a95
Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Commit-Id: ce0e2a014009390c4527e064efb59260ef4d3a3b
Original-Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a
Original-Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/45391
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2446609
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
Commit-Queue: Martin Roth <martinroth@google.com>
3 files changed
tree: 07abfc4f1a4ac2754a31a91384974eaed3a4210e
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. src/
  6. tests/
  7. util/
  8. .checkpatch.conf
  9. .clang-format
  10. .editorconfig
  11. .gitignore
  12. .gitmodules
  13. .gitreview
  14. AUTHORS
  15. COPYING
  16. gnat.adc
  17. MAINTAINERS
  18. Makefile
  19. Makefile.inc
  20. PRESUBMIT.cfg
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.