UPSTREAM: drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory region
APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record
Table) memory region:
* Bootloader (firmware) generates UEFI CPER (Common Platform Error
Record) records, and populates BERT region.
* OS parses ACPI BERT table, finds the BERT region address, inteprets
the data and processes it accordingly.
When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize,
so FSP allocates memory region for it. The APEI BERT region is placed
on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE.
Apart from APEI BERT region, we also have plan to add APEI HEST region
which holds OS runtime hardware error record, based on firmware
first hardware error handling model. HEST region will be reserved
same way as BERT region.
Note that CBMEM region can not be used for such purpose, the OS
(bert/hest) drivers are not able to access data held in CBMEM region,
as CBMEM is set as type 16 (configuration table).
An option considered was to reserve the BERT region under CBMEM.
However, we do not know the size of CBMEM till acpi tables are set up.
On the other hand, BERT region needs to be filled up before ACPI BERT
table is finalized.
BUG=none
BRANCH=none
TEST=none
Change-Id: I331b45b540b9e7cd8be634935dbc7bfa86405a95
Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Commit-Id: ce0e2a014009390c4527e064efb59260ef4d3a3b
Original-Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a
Original-Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/45391
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2446609
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
Commit-Queue: Martin Roth <martinroth@google.com>
diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c
index 0efb462..5388b89 100644
--- a/src/drivers/intel/fsp2_0/cbmem.c
+++ b/src/drivers/intel/fsp2_0/cbmem.c
@@ -6,7 +6,14 @@
void *cbmem_top_chipset(void)
{
struct range_entry tolum;
+ uint8_t *tolum_base;
fsp_find_bootloader_tolum(&tolum);
- return (void *)(uintptr_t)range_entry_end(&tolum);
+ tolum_base = (uint8_t *)(uintptr_t)range_entry_base(&tolum);
+
+ /*
+ * The TOLUM range may have other memory regions (such as APEI
+ * BERT region on top of CBMEM (IMD root and IMD small) region.
+ */
+ return tolum_base + cbmem_overhead_size();
}
diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c
index ec526e8..9bfb0f1 100644
--- a/src/drivers/intel/fsp2_0/hob_verify.c
+++ b/src/drivers/intel/fsp2_0/hob_verify.c
@@ -43,9 +43,16 @@
die("Space between FSP reserved region and BIOS TOLUM!\n");
}
- if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) {
+ if (!CONFIG(ACPI_BERT) && range_entry_end(&tolum) != (uintptr_t)cbmem_top()) {
printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n",
range_entry_end(&tolum), cbmem_top());
die("Space between cbmem_top and BIOS TOLUM!\n");
}
+
+ if (CONFIG(ACPI_BERT) &&
+ range_entry_end(&tolum) != (uintptr_t)cbmem_top() + CONFIG_ACPI_BERT_SIZE) {
+ printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top + 0x%x: BERT\n",
+ range_entry_end(&tolum), cbmem_top(), CONFIG_ACPI_BERT_SIZE);
+ die("Space between cbmem_top and APEI BERT!\n");
+ }
}
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 07c4463..1ef9324 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -276,6 +276,21 @@
/* Reserve enough memory under TOLUD to save CBMEM header */
arch_upd->BootLoaderTolumSize = cbmem_overhead_size();
+ /*
+ * If ACPI APEI BERT region size is defined, reserve memory for it.
+ * +------------------------+ range_entry_top(tolum)
+ * | Other reserved regions |
+ * | APEI BERT region |
+ * +------------------------+ cbmem_top()
+ * | CBMEM IMD ROOT |
+ * | CBMEM IMD SMALL |
+ * +------------------------+ range_entry_base(tolum), TOLUM
+ * | CBMEM FSP MEMORY |
+ * | Other CBMEM regions... |
+ */
+ if (CONFIG(ACPI_BERT))
+ arch_upd->BootLoaderTolumSize += CONFIG_ACPI_BERT_SIZE;
+
/* Fill common settings on behalf of chipset. */
if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
memmap) != CB_SUCCESS)
