UPSTREAM: soc/amd/stoneyridge: Call sb_spibase() early
Call sb_spibase() early so that it will set up the SPI base address.
This is another step to moving AGESA calls out of the bootblock.
BUG=b:74427893
BRANCH=master
TEST=Build and boot Grunt.
Change-Id: I1f4992f1bc68d26a34aaa06ce8714d1a7485c926
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 64294eb5e241afe9d93b37b31d8a6310ec8d9279
Original-Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0
Original-Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Original-Reviewed-on: https://review.coreboot.org/25246
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/968449
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index b4dcd8f..cf059a4 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -559,6 +559,7 @@
sb_enable_rom();
sb_lpc_port80();
sb_lpc_decode();
+ sb_spibase();
sb_acpi_mmio_decode();
enable_aoac_devices();
}
