| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| ## You should have received a copy of the GNU General Public License |
| ## along with this program; if not, write to the Free Software |
| ## Foundation, Inc. |
| ## |
| |
| config FSP_VENDORCODE_HEADER_PATH |
| string |
| default "fsp1_0/ivybridge_bd82x6x" if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X |
| default "fsp1_0/baytrail" if SOC_INTEL_FSP_BAYTRAIL |
| default "fsp1_0/rangeley" if CPU_INTEL_FSP_MODEL_406DX |
| |
| config UEFI_2_4_BINDING |
| def_bool n |
