UPSTREAM: google/fizz: correct memory rcomp settings
Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz
TEST= boot ok and the system can enter and resume from S3.
Change-Id: Iaffd54e328ef6c938b91750416e4e777bac3cf7f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 73031bcce071f6e760cc0655200dd3be2f39c8b7
Original-Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://review.coreboot.org/22479
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/789856
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c
index 405c4c1..335662e 100644
--- a/src/mainboard/google/fizz/romstage.c
+++ b/src/mainboard/google/fizz/romstage.c
@@ -24,9 +24,9 @@
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
/* Rcomp resistor */
- const u16 rcomp_resistor[] = { 200, 81, 162 };
+ const u16 rcomp_resistor[] = { 121, 81, 100 };
/* Rcomp target */
- const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
+ const u16 rcomp_target[] = { 100, 40, 20, 20, 26 };
/* SPD was saved in S0/S5 path, skips it when resumes from S3 */
if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME)
