commit | 3206430623b5ec4344dc83dfb3dfada12dd8396e | [log] [tgz] |
---|---|---|
author | Selma Bensaid <selma.bensaid@intel.com> | Thu Aug 25 15:35:14 2022 -0700 |
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Mon Oct 17 20:17:29 2022 +0000 |
tree | be82fd162479561fe69579cbf6f8d683c8d5046b | |
parent | 4d3dbfe886ace33d4ebc8e08ff6f40403c7faf96 [diff] |
UPSTREAM: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3301.03 The headers added are generated as per FSP v3301.03 In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:243693364 BRANCH=firmware-brya-14505.B TEST=Boot to OS (cherry picked from commit 8f2a647ec74570ee60f5f93451438cd75b04f651) Cq-Depend: chrome-internal:5028825 Original-Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Original-Change-Id: Idbd39ed53d4ba05248a0e83c104846960253931e Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/67084 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Original-Reviewed-by: Nick Vaccaro <nvaccaro@google.com> GitOrigin-RevId: 8f2a647ec74570ee60f5f93451438cd75b04f651 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3863659 Reviewed-by: YH Lin <yueherngl@chromium.org> Tested-by: Nick Vaccaro <nvaccaro@google.com> Commit-Queue: Nick Vaccaro <nvaccaro@google.com> Change-Id: I5cdb2fedabdb9e0ec1113bdbecb2a74fa1094780 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3946723 Tested-by: Ofer Fried <oferfried@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Commit-Queue: Ofer Fried <oferfried@google.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.