t210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0
The MC/SMMU should be resumed by the kernel. And the unexpected value
in the MC_INTSTATUS should be cleared before that. Or it will cause
some noisy MC interrupt once we enable the IRQ in the kernel.
BUG=chrome-os-partner:46796
BRANCH=none
TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors
should not be observed on resume.
Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/309248
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Joseph Lo <yushun.lo@gmail.com>
Tested-by: Joseph Lo <yushun.lo@gmail.com>
diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 1b18f3f..fc3d51a 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -333,6 +333,8 @@
static uint32_t *pmc_set_sw_clamp_ptr = (void *)(PMC_CTLR_BASE + 0x47c);
/* Memory controller registers. */
+static uint32_t *mc_intstatus_ptr = (void *)(MC_CTLR_BASE);
+static uint32_t *mc_intmask_ptr = (void *)(MC_CTLR_BASE + 0x4);
static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c);
static uint32_t *mc_video_protect_reg_ctrl_ptr =
@@ -869,6 +871,13 @@
write32(pmc_dpd_sample_ptr, 0);
udelay(10);
+ /* Clear the MC_INTSTATUS if MC_INTMASK was 0. */
+ if (!read32(mc_intmask_ptr)) {
+ uint32_t mc_intst_val = read32(mc_intstatus_ptr);
+ if (mc_intst_val)
+ write32(mc_intstatus_ptr, mc_intst_val);
+ }
+
/*
* Set both _ACCESS bits so that kernel/secure code
* can reconfig VPR careveout as needed from the TrustZone.
