| config SOC_NVIDIA_TEGRA132 |
| bool |
| default n |
| select ARCH_BOOTBLOCK_ARM_V4 |
| select ARCH_ROMSTAGE_ARM_V4 |
| select ARCH_RAMSTAGE_ARM_V8_64 |
| select ARM_LPAE |
| select BOOTBLOCK_CONSOLE |
| select HAVE_UART_SPECIAL |
| select HAVE_UART_MEMORY_MAPPED |
| select EARLY_CONSOLE |
| select ARM_BOOTBLOCK_CUSTOM |
| select DYNAMIC_CBMEM |
| |
| if SOC_NVIDIA_TEGRA132 |
| |
| config BOOTBLOCK_CPU_INIT |
| string |
| default "soc/nvidia/tegra132/bootblock.c" |
| help |
| CPU/SoC-specific bootblock code. This is useful if the |
| bootblock must load microcode or copy data from ROM before |
| searching for the bootblock. |
| |
| config BOOTBLOCK_ROM_OFFSET |
| hex |
| default 0x0 |
| |
| config CBFS_HEADER_ROM_OFFSET |
| hex "offset of master CBFS header in ROM" |
| default 0x22000 |
| |
| config CBFS_ROM_OFFSET |
| hex "offset of CBFS data in ROM" |
| default 0x22080 |
| |
| config BOOTBLOCK_BASE |
| hex |
| default 0x40020000 |
| |
| config ROMSTAGE_BASE |
| hex |
| default 0x4002c000 |
| |
| config SYS_SDRAM_BASE |
| hex |
| default 0x80000000 |
| |
| config RAMSTAGE_BASE |
| hex |
| default 0x80200000 |
| |
| config BOOTBLOCK_STACK_TOP |
| hex |
| default 0x40020000 |
| |
| config BOOTBLOCK_STACK_BOTTOM |
| hex |
| default 0x4001c000 |
| |
| config ROMSTAGE_STACK_TOP |
| hex |
| default 0x40020000 |
| |
| config ROMSTAGE_STACK_BOTTOM |
| hex |
| default 0x4001c000 |
| |
| config RAMSTAGE_STACK_TOP |
| hex |
| default 0x80020000 |
| |
| config RAMSTAGE_STACK_BOTTOM |
| hex |
| default 0x8001c000 |
| |
| config TTB_BUFFER |
| hex |
| default 0x80020000 |
| |
| config TTB_SIZE |
| hex |
| default 0x110000 |
| |
| config CBFS_CACHE_ADDRESS |
| hex "memory address to put CBFS cache data" |
| default 0x40006000 |
| |
| config CBFS_CACHE_SIZE |
| hex "size of CBFS cache data" |
| default 0x00016000 |
| |
| config CBMEM_CONSOLE_PRERAM_BASE |
| hex "memory address of the CBMEM console buffer" |
| default 0x40004020 |
| |
| choice CONSOLE_SERIAL_TEGRA132_UART_CHOICES |
| prompt "Serial Console UART" |
| default CONSOLE_SERIAL_TEGRA132_UARTA |
| depends on CONSOLE_SERIAL_UART |
| |
| config CONSOLE_SERIAL_TEGRA132_UARTA |
| bool "UARTA" |
| help |
| Serial console on UART A. |
| |
| config CONSOLE_SERIAL_TEGRA132_UARTB |
| bool "UARTB" |
| help |
| Serial console on UART B. |
| |
| config CONSOLE_SERIAL_TEGRA132_UARTC |
| bool "UARTC" |
| help |
| Serial console on UART C. |
| |
| config CONSOLE_SERIAL_TEGRA132_UARTD |
| bool "UARTD" |
| help |
| Serial console on UART D. |
| |
| config CONSOLE_SERIAL_TEGRA132_UARTE |
| bool "UARTE" |
| help |
| Serial console on UART E. |
| |
| endchoice |
| |
| config CONSOLE_SERIAL_TEGRA132_UART_ADDRESS |
| hex |
| depends on CONSOLE_SERIAL_UART |
| default 0x70006000 if CONSOLE_SERIAL_TEGRA132_UARTA |
| default 0x70006040 if CONSOLE_SERIAL_TEGRA132_UARTB |
| default 0x70006200 if CONSOLE_SERIAL_TEGRA132_UARTC |
| default 0x70006300 if CONSOLE_SERIAL_TEGRA132_UARTD |
| default 0x70006400 if CONSOLE_SERIAL_TEGRA132_UARTE |
| help |
| Map the UART names to the respective MMIO addres. |
| |
| config MTS_DIRECTORY |
| string "Directory where MTS microcode files are located" |
| default "." |
| help |
| Path to directory where MTS microcode files are located. |
| |
| config TRUSTZONE_CARVEOUT_SIZE_MB |
| hex "Size of Trust Zone region" |
| default 0x1 |
| help |
| Size of Trust Zone area in MiB to reserve in memory map. |
| |
| config BOOTROM_SDRAM_INIT |
| bool "SoC BootROM does SDRAM init with full BCT" |
| default n |
| help |
| Use during Ryu LPDDR3 bringup |
| |
| # Default to 700MHz. This value is based on nv bootloader setting. |
| config PLLX_KHZ |
| int |
| default 700000 |
| endif |
