UPSTREAM: soc/intel/alderlake: Add eMMC device into chipset.cb
Add eMMC device into chipset.cb and keep it `off` by default.
eMMC device is applicable only for Alder Lake N SOC.
BUG=none
BRANCH=none
TEST=none
Change-Id: I94b2c6a077b7da2badd6dd1cdce1a75a4358b575
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Original-Commit-Id: dbe92ead87f045aa33c4811be3ac77f17ba68413
Original-Change-Id: I2bc38ee5814688409feb7e4531c1daa5b54953c0
Original-Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/61065
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Subrata Banik <subratabanik@google.com>
Original-Reviewed-by: Kangheui Won <khwon@chromium.org>
Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3399994
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: Rob Barnes <robbarnes@google.com>
Commit-Queue: Rob Barnes <robbarnes@google.com>
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb
index c956fd4..e02cdad 100644
--- a/src/soc/intel/alderlake/chipset.cb
+++ b/src/soc/intel/alderlake/chipset.cb
@@ -185,6 +185,8 @@
device pci 19.0 alias i2c4 off end
device pci 19.1 alias i2c5 off end
device pci 19.2 alias uart2 off end
+ # eMMC device is applicable only for ADL-N
+ device pci 1a.0 alias emmc off end
device pci 1c.0 alias pcie_rp1 off end
device pci 1c.1 alias pcie_rp2 off end
device pci 1c.2 alias pcie_rp3 off end
