UPSTREAM: mb/google/poppy/variant/nocturne: add EC_SYNC_GPIO
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as
EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979
BRANCH=none
TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage",
flash & boot nocturne in dev mode, verify that volume up and down
buttons work in the dev screen and that the device boots properly into
the kernel.
Change-Id: I323b62bd08988a71b67d229dbd1847de6f752641
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 98189771abcf2a56a22f394de21bf512e88db608
Original-Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61
Original-Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1796475
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Commit-Queue: Nick Vaccaro <nvaccaro@google.com>
Tested-by: Nick Vaccaro <nvaccaro@google.com>
diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c
index cf9579e..1c5c180 100644
--- a/src/mainboard/google/poppy/chromeos.c
+++ b/src/mainboard/google/poppy/chromeos.c
@@ -35,6 +35,9 @@
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
"EC in RW"},
+#ifdef EC_SYNC_GPIO
+ {EC_SYNC_GPIO, ACTIVE_LOW, gpio_get(EC_SYNC_GPIO), "EC sync gpio"},
+#endif
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index d13cbc0..e66bb0e 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -196,7 +196,7 @@
/* D16 : ISH_UART0_CTS# ==> RCAM_RST_L */
PAD_CFG_GPO(GPP_D16, 0, DEEP),
/* D17 : DMIC_CLK1 ==> EC_PCH_ARCORE_INT_L */
- PAD_CFG_GPI_APIC(GPP_D17, NONE, PLTRST),
+ PAD_CFG_GPI_APIC_INVERT(GPP_D17, NONE, PLTRST),
/* D18 : DMIC_DATA1 ==> TP131 */
PAD_CFG_NC(GPP_D18),
/* D19 : DMIC_CLK0 ==> PCH_DMIC_CLK_OUT */
diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h
index fb7ad1a..45bb76b 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h
@@ -34,9 +34,12 @@
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
-/* EC sync irq is GPP_D12 */
+/* EC sync irq is tied to GPP_D17 */
#define EC_SYNC_IRQ GPP_D17_IRQ
+/* EC sync gpio */
+#define EC_SYNC_GPIO GPP_D17
+
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
