src/mainboard/opencellular/elgon/devicetree.cb

## SPDX-License-Identifier: GPL-2.0-only

chip soc/cavium/cn81xx
	device cpu_cluster 0 on end

	device domain 0 on
		chip soc/cavium/common/pci
			register "secure" = "0"
			device pci 01.0 on # PCI bridge
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 00.0 on end # MRML
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 00.1 on end # RESET
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 00.2 on end # DAP
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 00.3 on end # MDIO
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 00.4 on end # FUSE
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 01.2 on end # SGPIO
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 01.3 on end # SMI
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 01.4 on end # MMC
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 01.5 on end # KEY
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 01.6 on end # BOOT BUS
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 01.7 on end # PBUS
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 02.0 on end # XCV
				end
				device pci 04.0 on end

				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 06.0 on end # L2C-TAD
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 07.0 on end # L2C-CBC
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 07.4 on end # L2C-MCI
				end

				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 08.0 on end # UUA0
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 08.1 on end # UUA1
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 08.2 off end # UUA2
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 08.3 off end # UUA3
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 08.4 on end # VRM
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 09.0 on end # I2C0
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 09.1 on end # I2C1
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 0a.0 on end # PCC Bridge
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 0b.0 on end # IOBN
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 0c.0 on end # OCLA0
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 0c.1 on end # OCLA1
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 0d.0 on end
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 0e.0 on end # PCIe0
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 0e.1 on end # PCIe1
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 0e.2 on end # PCIe2
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 10.0 on end # bgx0
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 10.1 off end # bgx1
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 11.0 on end # rgx0
				end
				chip soc/cavium/common/pci
					register "secure" = "0"
					device pci 12.0 on end # MAC
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 1c.0 on end # GSER0
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 1c.1 on end # GSER1
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 1c.2 on end # GSER2
				end
				chip soc/cavium/common/pci
					register "secure" = "1"
					device pci 1c.3 on end # GSER3
				end
			end
			chip soc/cavium/common/pci
				register "secure" = "1"
				device pci 02.0 on end #SMMU
			end
			chip soc/cavium/common/pci
				register "secure" = "1"
				device pci 03.0 on end #GIC
			end
			chip soc/cavium/common/pci
				register "secure" = "1"
				device pci 04.0 on end #GTI
			end

			device pci 05.0 on end # NIC
			device pci 06.0 on end # GPIO
			device pci 07.0 on end # SPI
			device pci 08.0 on end # MIO
			device pci 09.0 on end # PCI bridge
			device pci 0a.0 on end # PCI bridge
			device pci 0b.0 on end # NFC
			device pci 0c.0 on end # PCI bridge
			device pci 0d.0 on end # PCM
			device pci 0e.0 on end # VRM
			device pci 0f.0 on end # PCI bridge

			device pci 10.0 on end # USB0
			device pci 11.0 on end # USB1
			device pci 16.0 on end # SATA0
			device pci 17.0 on end # SATA1
		end
	end
end