| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| */ |
| |
| #include <console/console.h> |
| #include <device/device.h> |
| #include <device/pci.h> |
| #include <arch/io.h> |
| #include <cpu/x86/msr.h> |
| #include <cpu/amd/mtrr.h> |
| #include <device/pci_def.h> |
| #include <southbridge/amd/sb600/sb600.h> |
| |
| #define ADT7461_ADDRESS 0x4C |
| #define ARA_ADDRESS 0x0C /* Alert Response Address */ |
| #define SMBUS_IO_BASE 0x1000 |
| |
| extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); |
| extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, |
| u8 val); |
| #define ADT7461_read_byte(address) \ |
| do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) |
| #define ARA_read_byte(address) \ |
| do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address) |
| #define ADT7461_write_byte(address, val) \ |
| do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) |
| |
| |
| |
| |
| /*************************************************** |
| * This board, the TIM-8690 has two Marvel 88e5056 PCI-E |
| * 10/100/1000 chips on board. |
| * Both of their pin PERSTn pins are connected to GPIO 5 of the |
| * SB600 southbridge. |
| ****************************************************/ |
| static void enable_onboard_nic(void) |
| { |
| |
| u8 byte; |
| device_t sm_dev; |
| |
| printk(BIOS_INFO, "enable_onboard_nic.\n"); |
| |
| sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| |
| byte = pci_read_config8(sm_dev, 0x9a); |
| byte |= ( 1 << 7); |
| pci_write_config8(sm_dev, 0x9a, byte); |
| |
| byte=pm_ioread(0x59); |
| byte &= ~( 1<< 5); |
| pm_iowrite(0x59,byte); |
| |
| byte = pci_read_config8(sm_dev, 0xA8); |
| |
| byte |= (1 << 1); //set bit 1 to high |
| pci_write_config8(sm_dev, 0xA8, byte); |
| } |
| |
| /* set thermal config |
| */ |
| static void set_thermal_config(void) |
| { |
| u8 byte; |
| u16 word; |
| device_t sm_dev; |
| |
| /* set ADT 7461 */ |
| ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ |
| ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */ |
| ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */ |
| ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */ |
| |
| ADT7461_write_byte(0x19, 0x55); /* External THERM limit */ |
| ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */ |
| |
| byte = ADT7461_read_byte(0x02); /* read status register to clear it */ |
| ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */ |
| printk(BIOS_INFO, "Init adt7461 end , status 0x02 %02x\n", byte); |
| |
| /* sb600 settings for thermal config */ |
| /* set SB600 GPIO 64 to GPIO with pull-up */ |
| byte = pm2_ioread(0x42); |
| byte &= 0x3f; |
| pm2_iowrite(0x42, byte); |
| |
| /* set GPIO 64 to input */ |
| sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| word = pci_read_config16(sm_dev, 0x56); |
| word |= 1 << 7; |
| pci_write_config16(sm_dev, 0x56, word); |
| |
| /* set GPIO 64 internal pull-up */ |
| byte = pm2_ioread(0xf0); |
| byte &= 0xee; |
| pm2_iowrite(0xf0, byte); |
| |
| /* set Talert to be active low */ |
| byte = pm_ioread(0x67); |
| byte &= ~(1 << 5); |
| pm_iowrite(0x67, byte); |
| |
| /* set Talert to generate ACPI event */ |
| byte = pm_ioread(0x3c); |
| byte &= 0xf3; |
| pm_iowrite(0x3c, byte); |
| |
| /* THERMTRIP pin */ |
| /* byte = pm_ioread(0x68); |
| * byte |= 1 << 3; |
| * pm_iowrite(0x68, byte); |
| * |
| * byte = pm_ioread(0x55); |
| * byte |= 1 << 0; |
| * pm_iowrite(0x55, byte); |
| * |
| * byte = pm_ioread(0x67); |
| * byte &= ~( 1 << 6); |
| * pm_iowrite(0x67, byte); |
| */ |
| } |
| |
| /************************************************* |
| * enable the dedicated function in tim8690 board. |
| * This function called early than rs690_enable. |
| *************************************************/ |
| static void mainboard_enable(device_t dev) |
| { |
| printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); |
| |
| enable_onboard_nic(); |
| set_thermal_config(); |
| } |
| |
| struct chip_operations mainboard_ops = { |
| .enable_dev = mainboard_enable, |
| }; |