commit bb11e60cb2f40da2a5a59dfacda4d46119ddda24
author Stefan Reinauer <reinauer@chromium.org> Thu May 10 12:15:18 2012 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Fri May 11 00:30:03 2012 +0200
tree f82bbd5b7af6cdae0b77e335db061f870900174f
parent 1244f4b52fe423eeac2621672aa1786232f2ca0b

Hook up MRC cache update

Requirements:
  - must be in ramstage (locking flash while executing code from there
    might not work)
  - must be after cbmem is reinitialized (so the mrc cache copy of the
    current run can be found)

Change-Id: I8028fb073349ce2b027ef5f8397dc1a1b8b31c02
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/boot/hardwaremain.c

diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index f0853ec..d78b859 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -130,6 +130,11 @@
 	timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
 	timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
 	timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+	timestamp_add_now(TS_CBMEM_POST);
+
+	if (cbmem_post_handling)
+		cbmem_post_handling();
+
 	timestamp_add_now(TS_WRITE_TABLES);
 
 	/* Now that we have collected all of our information

src/include/cbmem.h

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 33e2de4..a245232 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -73,6 +73,7 @@
 
 #ifndef __PRE_RAM__
 void set_cbmem_toc(struct cbmem_entry *);
+void __attribute__((weak)) cbmem_post_handling(void);
 #endif
 #endif
 #endif

src/include/timestamp.h

diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index 0bb323c..65bdf21 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -47,6 +47,7 @@
 	TS_DEVICE_ENABLE = 50,
 	TS_DEVICE_INITIALIZE = 60,
 	TS_DEVICE_DONE = 70,
+	TS_CBMEM_POST = 75,
 	TS_WRITE_TABLES = 80,
 	TS_LOAD_PAYLOAD = 90,
 	TS_ACPI_WAKE_JUMP = 98,

src/northbridge/intel/sandybridge/northbridge.c

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 7d7153e..6419f8c 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -33,6 +33,7 @@
 #include <bitops.h>
 #include <cpu/cpu.h>
 #include <boot/tables.h>
+#include <cbmem.h>
 #include "chip.h"
 #include "sandybridge.h"
 
@@ -77,7 +78,6 @@
 	return 0;
 }
 
-void cbmem_post_handling(void);
 void cbmem_post_handling(void)
 {
 	update_mrc_cache();
@@ -149,10 +149,6 @@
 	}
 }
 
-#if CONFIG_WRITE_HIGH_TABLES
-#include <cbmem.h>
-#endif
-
 static void pci_domain_set_resources(device_t dev)
 {
 	uint64_t tom, me_base, touud;