FSP: Use BOOTLOADER_TOLUM and FSP_RESERVED_MEMORY HOBs
Adjust the memory map to allow CBMEM root to be placed at the top of low
usable memory. The memory map routines start by determining the base of
TSEG. The routines then need to skip over the chipset reserved memory
region. The CONFIG_CHIPSET_RESERVED_MEM_BYTES value was added to make
this easier and to reduce the number of register references. The base
of the chipset reserved memory area is also the top of the CBMEM root
area.
Remove the use of CONFIG_FSP_RESERVED_MEM_SIZE.
Always validate that the FSP binary properly implements Sections 7.2 and
7.4 of the FSP 1.1 specification.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: Id4b3d25224217228194ce3404fff21d7a7e1da8c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
diff --git a/src/drivers/intel/fsp/Kconfig b/src/drivers/intel/fsp/Kconfig
index b5ac61d..480db8c 100644
--- a/src/drivers/intel/fsp/Kconfig
+++ b/src/drivers/intel/fsp/Kconfig
@@ -80,13 +80,6 @@
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
-config FSP_RESERVED_MEM_SIZE
- hex "FSP Reserved Memory"
- default 0x00100000
- help
- Memory size in bytes reserved by FSP between PEI Memory and the
- base of TSEG.
-
config ENABLE_FSP_FAST_BOOT
bool "Enable Fast Boot"
select ENABLE_MRC_CACHE
diff --git a/src/drivers/intel/fsp/fsp_hob.c b/src/drivers/intel/fsp/fsp_hob.c
index 39a57fb..5861937 100644
--- a/src/drivers/intel/fsp/fsp_hob.c
+++ b/src/drivers/intel/fsp/fsp_hob.c
@@ -417,72 +417,6 @@
printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n");
}
-/*
- * Locate the HOB containing the location of the fsp reserved mem area
- *
- * hob_list_ptr pointer to the start of the hob list
- *
- * Returns a pointer to the start of the FSP reserved memory or NULL if not
- * found
- */
-void *fsp_find_reserved_mem(void *hob_list_ptr)
-{
- EFI_GUID fsp_reserved_guid = FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
- EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem =
- (EFI_HOB_RESOURCE_DESCRIPTOR *) get_next_guid_hob(
- &fsp_reserved_guid, hob_list_ptr);
-
- if (fsp_reserved_mem == NULL) {
- printk(BIOS_ERR,
- "FSP_RESERVED_MEMORY_RESOURCE_HOB not found!\n");
- return NULL;
- }
-
- return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart);
-}
-
-void fsp_check_reserved_mem_size(void *hob_list_ptr, void *end_of_region)
-{
- EFI_HOB_GENERIC_HEADER *current_hob;
- EFI_HOB_MEMORY_ALLOCATION *alloc_hob;
- u8 list_end;
- uint32_t real_fsp_mem;
- uint32_t region_end;
- uint32_t fsp_base;
- uint64_t tmp_base;
-
- /* Determine the amount of memory below 4GB. */
- current_hob = hob_list_ptr;
- region_end = (uint32_t)end_of_region;
- fsp_base = region_end;
- do {
- if (current_hob->HobType == EFI_HOB_TYPE_MEMORY_ALLOCATION) {
- alloc_hob = (EFI_HOB_MEMORY_ALLOCATION *) current_hob;
- tmp_base = alloc_hob->AllocDescriptor.MemoryBaseAddress;
- if (tmp_base < fsp_base)
- fsp_base = (uint32_t)tmp_base;
- }
-
- list_end = END_OF_HOB_LIST(current_hob);
- if (!list_end)
- current_hob = GET_NEXT_HOB(current_hob);
- } while (!list_end);
-
- /* Next detemine how much memory was reserved by FSP. */
- real_fsp_mem = region_end - fsp_base;
- printk(BIOS_DEBUG, "CBMEM TOP: 0x%08x\n", fsp_base);
- printk(BIOS_DEBUG, "FSP Reserved: 0x%08x\n", real_fsp_mem);
- printk(BIOS_DEBUG, "Firmware Expected: 0x%08x\n",
- CONFIG_FSP_RESERVED_MEM_SIZE);
- if (real_fsp_mem > CONFIG_FSP_RESERVED_MEM_SIZE) {
- printk(BIOS_DEBUG,
- "Update CONFIG_FSP_RESERVED_MEM_SIZE >= 0x%08x",
- real_fsp_mem);
- while (1)
- hlt();
- }
-}
-
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
/*
* Save the FSP memory HOB (mrc data) to the MRC area in CBMEM
diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h
index 203ef16..143b637 100644
--- a/src/drivers/intel/fsp/fsp_util.h
+++ b/src/drivers/intel/fsp/fsp_util.h
@@ -55,8 +55,6 @@
/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */
void *fsp_get_hob_list(void);
void fsp_early_init(FSP_INFO_HEADER *fsp_info);
-void fsp_check_reserved_mem_size(void *hob_list_ptr, void* end_of_region);
-void *fsp_find_reserved_mem(void *hob_list_ptr);
void fsp_notify(u32 phase);
void print_hob_type_structure(u16 hob_type, void *hob_list_ptr);
void print_fsp_info(FSP_INFO_HEADER *fsp_header);
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index 1abf7f0..7edc26d 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -52,6 +52,34 @@
char *smm_base;
size_t smm_size;
+ /*
+ * +-------------------------+ Top of RAM (aligned)
+ * | System Management Mode |
+ * | code and data | Length: CONFIG_TSEG_SIZE
+ * | (TSEG) |
+ * +-------------------------+ SMM base (aligned)
+ * | |
+ * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
+ * | |
+ * +-------------------------+ top_of_ram (aligned)
+ * | |
+ * | CBMEM Root |
+ * | |
+ * +-------------------------+
+ * | |
+ * | FSP Reserved Memory |
+ * | |
+ * +-------------------------+
+ * | |
+ * | Various CBMEM Entries |
+ * | |
+ * +-------------------------+ top_of_stack (8 byte aligned)
+ * | |
+ * | stack (CBMEM Entry) |
+ * | |
+ * +-------------------------+
+ */
+
smm_region((void **)&smm_base, &smm_size);
- return (void *)(smm_base - CONFIG_FSP_RESERVED_MEM_SIZE);
+ return smm_base - CONFIG_CHIPSET_RESERVED_MEM_BYTES;
}
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index e162585..fda58ae 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -52,7 +52,7 @@
* | TSEG |
* +--------------------------+ SMMRRL
* | FSP Reserved Mem |
- * +--------------------------+ SMMRRL - FSP_RESERVED_MEM_SIZE
+ * +--------------------------+ SMMRRL - CONFIG_CHIPSET_RESERVED_MEM_BYTES
* | Usable DRAM |
* +--------------------------+ 0
*
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index dd48565..230e9de 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -38,8 +38,8 @@
tom -= (dpr & DPR_SIZE_MASK) << 16;
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
- /* Allocate some space for FSP */
- tom -= CONFIG_FSP_RESERVED_MEM_SIZE;
+ /* Allocate any extra space for the chipset */
+ tom -= CONFIG_CHIPSET_RESERVED_MEM_BYTES;
#endif /* CONFIG_PLATFORM_USES_FSP */
return (unsigned long)tom;
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index eceefd7..40afe5d 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -349,7 +349,7 @@
size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
size_k -= dpr_size >> 10;
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
- size_k -= CONFIG_FSP_RESERVED_MEM_SIZE >> 10;
+ size_k -= CONFIG_CHIPSET_RESERVED_MEM_BYTES >> 10;
#endif /* CONFIG_PLATFORM_USES_FSP */
ram_resource(dev, index++, base_k, size_k);
@@ -358,8 +358,8 @@
resource->base = mc_values[TSEG_REG] - dpr_size;
resource->size = mc_values[BGSM_REG] - resource->base;
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP)
- resource->base -= CONFIG_FSP_RESERVED_MEM_SIZE;
- resource->size += CONFIG_FSP_RESERVED_MEM_SIZE;
+ resource->base -= CONFIG_CHIPSET_RESERVED_MEM_BYTES;
+ resource->size += CONFIG_CHIPSET_RESERVED_MEM_BYTES;
#endif /* CONFIG_PLATFORM_USES_FSP */
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_RESERVE |
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig
index 5747b6b..f556fb0 100644
--- a/src/soc/intel/common/Kconfig
+++ b/src/soc/intel/common/Kconfig
@@ -29,6 +29,18 @@
endif # HAVE_MRC
+config CHIPSET_RESERVED_MEM_BYTES
+ hex "Size in bytes of chipset reserved memory area"
+ default 0
+ help
+ If insufficient documentation is available to determine the size of
+ the chipset reserved memory area by walking the chipset registers,
+ the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account
+ for the missing pieces of memory. The value specified in bytes is:
+
+ value = TSEG base - top of low usable memory - (any sizes determined
+ by reading chipset registers)
+
config COMMON_STACK
bool
default n
diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c
index 3be3666..a322d47 100644
--- a/src/soc/intel/common/fsp_ramstage.c
+++ b/src/soc/intel/common/fsp_ramstage.c
@@ -68,6 +68,32 @@
status = fsp_silicon_init(NULL);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
+
+#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
+ /* Verify the HOBs */
+ const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
+ void *hob_list_ptr = get_hob_list();
+ int missing_hob = 0;
+
+ if (hob_list_ptr == NULL)
+ die("ERROR - HOB pointer is NULL!\n");
+ print_hob_type_structure(0, hob_list_ptr);
+
+ /*
+ * Verify that FSP is generating the required HOBs:
+ * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
+ * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
+ * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
+ * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
+ */
+ if (NULL == get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) {
+ printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
+ missing_hob = 1;
+ }
+ if (missing_hob)
+ die("ERROR - Missing one or more required FSP HOBs!\n");
+#endif
+
soc_after_silicon_init();
}
diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c
index 765c6bd..38c7f3e 100644
--- a/src/soc/intel/common/raminit.c
+++ b/src/soc/intel/common/raminit.c
@@ -30,27 +30,28 @@
void raminit(struct romstage_params *params)
{
+ const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
+ EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
FSP_INFO_HEADER *fsp_header;
EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory;
FSP_MEMORY_INIT fsp_memory_init;
FSP_MEMORY_INIT_PARAMS fsp_memory_init_params;
const EFI_GUID fsp_reserved_guid =
FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
+ void *fsp_reserved_memory_area;
FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer;
void *hob_list_ptr;
const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
u32 *mrc_hob;
+ u32 fsp_reserved_bytes;
EFI_STATUS status;
struct pei_data *pei_ptr;
VPD_DATA_REGION *vpd_ptr;
UPD_DATA_REGION *upd_ptr;
UPD_DATA_REGION upd_data_buffer;
+ int fsp_verification_failure = 0;
#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
- const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
- EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
unsigned long int data;
- void *fsp_reserved_memory_area;
- int missing_hob = 0;
EFI_PEI_HOB_POINTERS hob_ptr;
#endif
@@ -122,11 +123,17 @@
die("ERROR - FspMemoryInit failed to initialize memory!\n");
/* Locate the FSP reserved memory area */
+ fsp_reserved_bytes = 0;
fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr);
- if (fsp_memory == NULL)
- die("FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n");
- printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n",
- (unsigned long int)fsp_memory->ResourceLength);
+ if (fsp_memory == NULL) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG,
+ "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n");
+ } else {
+ fsp_reserved_bytes = fsp_memory->ResourceLength;
+ printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n",
+ (unsigned long int)fsp_reserved_bytes);
+ }
/* Display SMM area */
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
@@ -139,12 +146,14 @@
#endif
/* Migrate CAR data */
+ printk(BIOS_DEBUG, "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n",
+ CONFIG_CHIPSET_RESERVED_MEM_BYTES);
printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
- fsp_memory->ResourceLength);
+ fsp_reserved_bytes);
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
- fsp_memory->ResourceLength)) {
+ fsp_reserved_bytes)) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
@@ -155,6 +164,15 @@
/* Save the FSP runtime parameters. */
fsp_set_runtime(params->chipset_context, hob_list_ptr);
+ /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */
+ cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);
+ if (cbmem_root == NULL) {
+ fsp_verification_failure = 1;
+ printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n");
+ printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n",
+ fsp_rt_common_buffer.BootLoaderTolumSize);
+ }
+
#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
if (hob_list_ptr == NULL)
die("ERROR - HOB pointer is NULL!\n");
@@ -164,62 +182,82 @@
* 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
* 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
*/
- cbmem_root = NULL;
- hob_ptr.Raw = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);
- if ((NULL == hob_ptr.Raw)
- && (fsp_rt_common_buffer.BootLoaderTolumSize != 0)) {
- printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n");
- printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n",
- fsp_rt_common_buffer.BootLoaderTolumSize);
- missing_hob = 1;
- } else {
+ if (NULL != cbmem_root) {
printk(BIOS_DEBUG,
"7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
- hob_ptr.Raw);
- data = hob_ptr.ResourceDescriptor->PhysicalStart;
+ cbmem_root);
+ data = cbmem_root->PhysicalStart;
printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
- data = hob_ptr.ResourceDescriptor->ResourceLength;
+ data = cbmem_root->ResourceLength;
printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
- cbmem_root = hob_ptr.ResourceDescriptor;
}
hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
if (NULL == hob_ptr.Raw) {
printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
- missing_hob = 1;
+ fsp_verification_failure =
+ (params->pei_data->saved_data == NULL) ? 1 : 0;
} else {
printk(BIOS_DEBUG,
"7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n",
hob_ptr.Raw);
}
- printk(BIOS_DEBUG,
- "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n",
- fsp_memory);
- data = fsp_memory->PhysicalStart;
- printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
- data = fsp_memory->ResourceLength;
- printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
+ if (fsp_memory != NULL) {
+ printk(BIOS_DEBUG,
+ "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n",
+ fsp_memory);
+ data = fsp_memory->PhysicalStart;
+ printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
+ data = fsp_memory->ResourceLength;
+ printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
+ }
+
+ /* Verify all the HOBs are present */
+ if (fsp_verification_failure)
+ printk(BIOS_DEBUG,
+ "ERROR - Missing one or more required FSP HOBs!\n");
+
+ /* Display the HOBs */
+ print_hob_type_structure(0, hob_list_ptr);
+#endif
+
+ /* Get the address of the CBMEM region for the FSP reserved memory */
fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n",
fsp_reserved_memory_area);
- /* Display the HOBs */
- print_hob_type_structure(0, hob_list_ptr);
+ /* Verify the order of CBMEM root and FSP memory */
+ if ((fsp_memory != NULL) && (cbmem_root != NULL) &&
+ (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG,
+ "ERROR - FSP reserved memory above CBMEM root!\n");
+ }
/* Verify that the FSP memory was properly reserved */
if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) ||
- (cbmem_root->PhysicalStart !=
- (unsigned int)fsp_reserved_memory_area)))
- die("ERROR - Reserving FSP memory area!\n");
-
- /* Verify the order of CBMEM root and FSP memory */
- if ((fsp_memory != NULL) && (cbmem_root != NULL) &&
- (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart))
- die("ERROR - FSP reserved memory above CBMEM root!\n");
-
- /* Verify all the HOBs are present */
- if (missing_hob)
- die("ERROR - Missing one or more required FSP HOBs!\n");
+ (fsp_memory->PhysicalStart !=
+ (unsigned int)fsp_reserved_memory_area))) {
+ fsp_verification_failure = 1;
+ printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ if (cbmem_root != NULL) {
+ size_t delta_bytes = (unsigned int)smm_base
+ - cbmem_root->PhysicalStart
+ - cbmem_root->ResourceLength;
+ printk(BIOS_DEBUG,
+ "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n",
+ CONFIG_CHIPSET_RESERVED_MEM_BYTES);
+ printk(BIOS_DEBUG,
+ "0x%08x: Chipset reserved bytes reported by FSP\n",
+ delta_bytes);
+ die("Please verify the chipset reserved size\n");
+ }
#endif
+ }
+
+ /* Verify the FSP 1.1 HOB interface */
+ if (fsp_verification_failure)
+ die("ERROR - Coreboot's requirements not met by FSP binary!\n");
/* Display the memory configuration */
report_memory_config();
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index 46c571a..96a73e0 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -202,31 +202,6 @@
asmlinkage void romstage_after_car(void *chipset_context)
{
- /* Verify the HOBs */
-#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
- const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
- void *hob_list_ptr = get_hob_list();
- int missing_hob = 0;
-
- if (hob_list_ptr == NULL)
- die("ERROR - HOB pointer is NULL!\n");
- print_hob_type_structure(0, hob_list_ptr);
-
- /*
- * Verify that FSP is generating the required HOBs:
- * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
- * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit
- * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit
- * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit
- */
- if (NULL == get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) {
- printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n");
- missing_hob = 1;
- }
- if (missing_hob)
- die("ERROR - Missing one or more required FSP HOBs!\n");
-#endif
-
if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP)) {
timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
diff --git a/src/soc/intel/common/stack.c b/src/soc/intel/common/stack.c
index 3e6e4b7..03cf30c 100644
--- a/src/soc/intel/common/stack.c
+++ b/src/soc/intel/common/stack.c
@@ -103,18 +103,18 @@
* | (TSEG) |
* +-------------------------+ SMM base (aligned)
* | |
- * | Chipset Reserved Memory |
+ * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
* | |
- * +-------------------------+ Chipset reserved mem base (aligned)
- * | |
- * | FSP Reserved Memory |
- * | |
- * +-------------------------+ top_of_ram (not aligned)
+ * +-------------------------+ top_of_ram (aligned)
* | |
* | CBMEM Root |
* | |
* +-------------------------+
* | |
+ * | FSP Reserved Memory |
+ * | |
+ * +-------------------------+
+ * | |
* | Various CBMEM Entries |
* | |
* +-------------------------+ top_of_stack (8 byte aligned)
@@ -122,11 +122,6 @@
* | stack (CBMEM Entry) |
* | |
* +-------------------------+
- *
- * Requirement:
- * Chipset reserved memory base needs to be aligned to a multiple
- * of TSEG size when SMM is in use or 8 Mib when SMM is not supported
- * by the SOC/board configuration.
*/
/*
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index cc579ef..fc4a727 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -64,18 +64,18 @@
* | (TSEG) |
* +-------------------------+ SMM base (aligned)
* | |
- * | Chipset Reserved Memory |
+ * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
* | |
- * +-------------------------+ Chipset reserved mem base (aligned)
- * | |
- * | FSP Reserved Memory |
- * | |
- * +-------------------------+ top_of_ram (not aligned)
+ * +-------------------------+ top_of_ram (aligned)
* | |
* | CBMEM Root |
* | |
* +-------------------------+
* | |
+ * | FSP Reserved Memory |
+ * | |
+ * +-------------------------+
+ * | |
* | Various CBMEM Entries |
* | |
* +-------------------------+ top_of_stack (8 byte aligned)
@@ -83,14 +83,10 @@
* | stack (CBMEM Entry) |
* | |
* +-------------------------+
- *
- * Requirement:
- * Chipset reserved memory base needs to be aligned to a multiple
- * of TSEG size when SMM is in use or 8 Mib when SMM is not supported
- * by the SOC/board configuration.
*/
unsigned long top_of_ram = (unsigned long)smm_region_start();
+
/*
* Subtract DMA Protected Range size if enabled and align to a multiple
* of TSEG size.
@@ -101,9 +97,6 @@
top_of_ram = ALIGN_DOWN(top_of_ram, mmap_region_granluarity());
}
- /* Allocate some space for FSP */
- top_of_ram -= CONFIG_FSP_RESERVED_MEM_SIZE;
-
- return (void *)top_of_ram;
+ return (void *)(top_of_ram - CONFIG_CHIPSET_RESERVED_MEM_BYTES);
}
