UPSTREAM: soc/intel/skylake: Add SATA interrupt for APIC mode
Add SATA interrupt for APIC mode
BUG=none
BRANCH=none
TEST=none
Change-Id: Ied09c5580cb3ce3ac4673c4191e58462ff585c41
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 951ec96f17100692daed8c5316ffa13a7ed387d9
Original-Change-Id: I9e0682e235715399da2c585174925c89b9116ab3
Original-Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18130
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/430734
diff --git a/src/soc/intel/skylake/acpi/pci_irqs.asl b/src/soc/intel/skylake/acpi/pci_irqs.asl
index 41e1a9d..eb10b36 100644
--- a/src/soc/intel/skylake/acpi/pci_irqs.asl
+++ b/src/soc/intel/skylake/acpi/pci_irqs.asl
@@ -48,6 +48,8 @@
Package () { 0x0016FFFF, 1, 0, HECI_2_IRQ },
Package () { 0x0016FFFF, 2, 0, IDER_IRQ },
Package () { 0x0016FFFF, 3, 0, KT_IRQ },
+ /* D23: Sata controller */
+ Package () { 0x0017FFFF, 0, 0, SATA_IRQ },
/* D21: SerialIo */
Package () { 0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
Package () { 0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
