UPSTREAM: mb/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C displays for TGL-Y RVP
- Enable DDC pins for DDI-B
- Enable HPD pins for DDI-1/DDI-2
- Update MPHY/USB2 Mapping to match with the TGL-Y RVP schematic
BUG: System not able to detect displays attached to onboard micro-HDMI or Type-C connectors
TEST: hot-plug/unplug HDMI displays with onboard micro-HDMI connector and USB Type-C connectors to make sure the displays get detected and enabled
BUG=none
BRANCH=none
TEST=none
Change-Id: I325f469fa8b6d0e9f3d52ec02e3c5b65589fa642
Signed-off-by: Martin Roth <gaumless@gmail.com>
Original-Commit-Id: 2b3416134fa2f1400b764666dd7f1953915029a8
Original-Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935
Original-Signed-off-by: Jason Le <jason.v.le@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/45016
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2445927
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
Commit-Queue: Martin Roth <martinroth@google.com>
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 3e2b342..842ae68 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -21,10 +21,13 @@
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
- register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1
- register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
- register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used
+ register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
@@ -65,9 +68,16 @@
# enabling EDP in PortA
register "DdiPortAConfig" = "1"
+ register "DdiPortAHpd" = "1"
+ register "DdiPortADdc" = "0"
register "DdiPortBHpd" = "1"
+ register "DdiPortBDdc" = "1"
+ register "DdiPortCHpd" = "0"
+ register "DdiPortCDdc" = "0"
register "DdiPort1Hpd" = "1"
- register "DdiPort1Ddc" = "1"
+ register "DdiPort1Ddc" = "0"
+ register "DdiPort2Hpd" = "1"
+ register "DdiPort2Ddc" = "0"
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
