exynos5420/pit/kirby: re-factor membaseconfig0/1 usage
membaseconfig0/1 are utterly dependent on the mainboard's particular
DRAM setup. This defines their values in the mem_timings struct for
pit and kirby.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=none
TEST=booted on pit, ran /usr/local/opt/punybench/bin/memcpy_test -b,
tested on kirby in follow-up patch
Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
Reviewed-on: https://chromium-review.googlesource.com/167488
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 1126dca..1d7b8a8 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -145,21 +145,15 @@
update_reset_dll(drex0, DDR_MODE_DDR3);
update_reset_dll(drex1, DDR_MODE_DDR3);
- /* Set Base Address:
- * 0x2000_0000 ~ 0x5FFF_FFFF
- * 0x6000_0000 ~ 0x9FFF_FFFF
- */
- /* MEMBASECONFIG0 */
- val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_0) |
- DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig0);
- writel(val, &tzasc1->membaseconfig0);
+ /* MEMBASECONFIG0 (CS0) */
+ writel(mem->membaseconfig0, &tzasc0->membaseconfig0);
+ writel(mem->membaseconfig0, &tzasc1->membaseconfig0);
- /* MEMBASECONFIG1 */
- val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_1) |
- DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig1);
- writel(val, &tzasc1->membaseconfig1);
+ /* MEMBASECONFIG1 (CS1) */
+ if (mem->chips_per_channel == 2) {
+ writel(mem->membaseconfig1, &tzasc0->membaseconfig1);
+ writel(mem->membaseconfig1, &tzasc1->membaseconfig1);
+ }
/* Memory Channel Inteleaving Size
* Exynos5420 Channel interleaving = 128 bytes
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 3bd36b2..0179f3d 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -767,15 +767,12 @@
#define DPWRDN_EN (1 << 1)
#define DSREF_EN (1 << 5)
-/* As we use channel interleaving, therefore value of the base address
- * register must be set as half of the bus base address
- * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
- * we need to set half 0x10 to the membaseconfigx registers
- * see exynos5420 UM section 17.17.3.21 for more
- */
-#define DMC_CHIP_BASE_0 0x10
-#define DMC_CHIP_BASE_1 0x50
-#define DMC_CHIP_MASK 0x7C0
+/* AXI base address mask */
+#define DMC_CHIP_MASK_256MB 0x7f0
+#define DMC_CHIP_MASK_512MB 0x7e0
+#define DMC_CHIP_MASK_1GB 0x7c0
+#define DMC_CHIP_MASK_2GB 0x780
+#define DMC_CHIP_MASK_4GB 0x700
#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
diff --git a/src/mainboard/google/kirby/memory.c b/src/mainboard/google/kirby/memory.c
index 4ef418f..bd4af93 100644
--- a/src/mainboard/google/kirby/memory.c
+++ b/src/mainboard/google/kirby/memory.c
@@ -90,6 +90,13 @@
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
+ /*
+ * For channel interleaving, the chip_base needs to be set to
+ * half the bus address. So for a base address of 0x2000_0000,
+ * the chip_base value is 0x20 without interleaving and 0x10
+ * with channel interleaving. See note in section 17.14.
+ */
+ .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_2GB,
.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
DMC_MEMCONFIGx_CHIP_COL_10 |
DMC_MEMCONFIGx_CHIP_ROW_15 |
diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c
index 4ac3d0c..0c30773 100644
--- a/src/mainboard/google/pit/memory.c
+++ b/src/mainboard/google/pit/memory.c
@@ -90,6 +90,13 @@
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
+ /*
+ * For channel interleaving, the chip_base needs to be set to
+ * half the bus address. So for a base address of 0x2000_0000,
+ * the chip_base value is 0x20 without interleaving and 0x10
+ * with channel interleaving. See note in section 17.14.
+ */
+ .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
DMC_MEMCONFIGx_CHIP_COL_10 |
DMC_MEMCONFIGx_CHIP_ROW_15 |
