UPSTREAM: mb/google/octopus/var/fleex: Add ssfc codec cs42l42 support
Add cs42l42 codec support in fleex.
BUG=b:184103445
TEST=boot to check cs42l42 is functional.
Change-Id: Id9306f6a4cf396f4f8f247a633d25f388d8a058d
Original-Commit-Id: 598f2babdcff16698b5928126f7cd8203120a8ea
Original-Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Original-Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2847972
(cherry picked from commit 7f6766032aa496b6eba431b702a19deb671eb26b)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2848724
Commit-Queue: Henry Sun <henrysun@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: Henry Sun <henrysun@google.com>
(cherry picked from commit 7fe9487983ce239f62450c2c0d0c1719f9d4d4b3)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2859558
Tested-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Auto-Submit: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@chromium.org>
Commit-Queue: Marco Chen <marcochen@chromium.org>
diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig
index 5718109..4df11e4 100644
--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -5,6 +5,7 @@
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_GPIO_KEYS
select DRIVERS_GENERIC_MAX98357A
+ select DRIVERS_I2C_CS42L42
select DRIVERS_I2C_DA7219
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c
index b8579ac..e565f28 100644
--- a/src/mainboard/google/octopus/mainboard.c
+++ b/src/mainboard/google/octopus/mainboard.c
@@ -37,6 +37,7 @@
#include <variant/gpio.h>
extern struct chip_operations drivers_i2c_generic_ops;
+extern struct chip_operations drivers_i2c_cs42l42_ops;
extern struct chip_operations drivers_i2c_da7219_ops;
static bool is_cnvi_held_in_reset(void)
@@ -212,6 +213,13 @@
continue;
}
}
+
+ if ((audio_dev->chip_ops == &drivers_i2c_cs42l42_ops) &&
+ (codec == SSFC_AUDIO_CODEC_CS42L42)) {
+ printk(BIOS_INFO, "enable CS42L42.\n");
+ continue;
+ }
+
printk(BIOS_INFO, "%s has been disabled\n", audio_dev->chip_ops->name);
audio_dev->enabled = 0;
}
diff --git a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h
index 84020d7..cef047a 100644
--- a/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h
+++ b/src/mainboard/google/octopus/variants/baseboard/include/baseboard/cbi_ssfc.h
@@ -29,6 +29,7 @@
SSFC_AUDIO_CODEC_DEFAULT,
SSFC_AUDIO_CODEC_DA7219,
SSFC_AUDIO_CODEC_RT5682,
+ SSFC_AUDIO_CODEC_CS42L42,
};
#define SSFC_AUDIO_CODEC_OFFSET 9
#define SSFC_AUDIO_CODEC_MASK 0x7
diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c
index c383630..cf0c488 100644
--- a/src/mainboard/google/octopus/variants/fleex/gpio.c
+++ b/src/mainboard/google/octopus/variants/fleex/gpio.c
@@ -29,7 +29,8 @@
PAD_CFG_GPO(GPIO_117, 1, PWROK),
PAD_NC(GPIO_143, UP_20K),
- PAD_NC(GPIO_144, UP_20K),
+ /* GPIO_144 -- Codec reset pin. */
+ PAD_CFG_GPO(GPIO_144, 1, PWROK),
PAD_NC(GPIO_145, UP_20K),
/* EN_PP3300_TOUCHSCREEN */
diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
index 77cce86..9c321a7 100644
--- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb
@@ -122,6 +122,21 @@
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
+ chip drivers/i2c/cs42l42
+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_144)"
+ register "ts_inv" = "true"
+ register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
+ register "ts_dbnc_fall" = "FALL_DEB_0_MS"
+ register "btn_det_init_dbnce" = "100"
+ register "btn_det_event_dbnce" = "10"
+ register "bias_lvls[0]" = "15"
+ register "bias_lvls[1]" = "8"
+ register "bias_lvls[2]" = "4"
+ register "bias_lvls[3]" = "1"
+ register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
+ device i2c 48 on end
+ end
end # - I2C 5
device pci 17.2 on
chip drivers/i2c/generic
