| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved. |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License as |
| * published by the Free Software Foundation; version 2 of |
| * the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| * MA 02110-1301 USA |
| */ |
| |
| /* Included in each PCIe Root Port device */ |
| |
| OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) |
| Field (RPCS, AnyAcc, NoLock, Preserve) |
| { |
| Offset (0x4c), // Link Capabilities |
| , 24, |
| RPPN, 8, // Root Port Number |
| } |
