commit 57a5d90d394086483e0dcdd6279678658d07d842
author huang lin <hl@rock-chips.com> Fri Oct 10 23:26:21 2014 -0700
committer chrome-internal-fetch <chrome-internal-fetch@google.com> Wed Oct 15 18:23:07 2014 +0000
tree 8f665c98d5f84c633734257ae2c66c004f078fe2
parent a06b36f9003d801709d83a8faed6fc04bb91df1b

rk3288: guarantee i2c low period more than 1.3us

       change i2c clock low period and high perid propoton to 7:3
       guarantee the low period more than 1.3us

BUG=None
TEST=Boot on veyron_pinky rev2,check the i2c clock frequency

Change-Id: I235e9e3ff54ab3b9cabad36bab58a8409f7005a0
Signed-off-by: huang lin <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/223002
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/soc/rockchip/rk3288/i2c.c

diff --git a/src/soc/rockchip/rk3288/i2c.c b/src/soc/rockchip/rk3288/i2c.c
index 142ec4a..eb480a7 100644
--- a/src/soc/rockchip/rk3288/i2c.c
+++ b/src/soc/rockchip/rk3288/i2c.c
@@ -284,7 +284,7 @@
 	unsigned int clk_div;
 	unsigned int divl;
 	unsigned int divh;
-	unsigned int i2c_src_clk;
+	unsigned int i2c_src_clk = 0;
 	struct rk3288_i2c_regs *regs = i2c_bus[bus];
 
 	/*i2c0,i2c2 src clk from pd_bus_pclk
@@ -308,9 +308,9 @@
 	/*SCL Divisor = 8*(CLKDIVL + 1 + CLKDIVH + 1)
 	  SCL = PCLK/ SCLK Divisor
 	*/
-	clk_div = div_round_up(i2c_src_clk, hz * 8) - 2;
-	divh = clk_div / 2;
-	divl = ALIGN_UP(clk_div, 2) / 2;
+	clk_div = div_round_up(i2c_src_clk, hz * 8);
+	divh = clk_div * 3 / 7 - 1;
+	divl = clk_div - divh - 2;
 	assert((divh < 65536) && (divl < 65536));
 	writel((divh << 16) | (divl << 0), &regs->i2c_clkdiv);
 }