baytrail: adjust cache policy during romstage
The caching policy for romstage was previously using a 32KiB
of cache-as-ram for both the MRC wrapper and the romstage stack/data.
It also used a 32KiB code cache region. The BWG's limitations for
the code and data region before memory is up was wrong. It consists
of a 16-way set associative 1MiB cache. As long as enough addresses
are not read there isn't a risk of evicting the data/stack.
Now create a 64KiB cache-as-ram region split evenly between romstage
and the MRC wrapper. Additionally cache the memory just below
4GiB in CBFS size. This will cover any code and read-only data needed.
BUG=chrome-os-partner:22858
BRANCH=None
TEST=Built and booted quickly with corresponding changes to MRC warpper.
CQ-DEPEND=CL:*146175
Change-Id: I021cecb886a9c0622005edc389136d22905d4520
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172150
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index aeb468a..6e1991b 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -94,15 +94,6 @@
endif # HAVE_MRC
-config CAR_TILE_SIZE
- hex
- default 0x8000
- help
- The tile size is the limit that can be assigned to cache-as-ram
- region as well as the amount of code cache used during cache-as-ram.
- Also note that (DCACHE_RAM_BASE ^ MRC_BIN_ADDRESS) & CAR_TILE_SIZE ==
- CAR_TILE_SIZE.
-
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
@@ -125,11 +116,11 @@
config DCACHE_RAM_BASE
hex
- default 0xff7f8000
+ default 0xff800000
config DCACHE_RAM_SIZE
hex
- default 0x1000
+ default 0x8000
help
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
@@ -137,7 +128,7 @@
config DCACHE_RAM_MRC_VAR_SIZE
hex
- default 0x7000
+ default 0x8000
help
The amount of cache-as-ram region required by the reference code.
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index 557e123..1d49af5 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -31,10 +31,10 @@
(CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-/* Enough room to cache CAR_TILE_SIZE starting at MRC_BIN_ADDRESS */
-#define CACHE_MRC_BASE (CONFIG_MRC_BIN_ADDRESS)
-#define CACHE_MRC_MASK (~(CONFIG_CAR_TILE_SIZE - 1))
-
+/* Cache all of CBFS just below 4GiB as Write-Protect type. */
+#define CODE_CACHE_SIZE (CONFIG_CBFS_SIZE)
+#define CODE_CACHE_BASE (-CODE_CACHE_SIZE)
+#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1))
#define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1)
#define NoEvictMod_MSR 0x2e0
@@ -109,14 +109,14 @@
wrmsr
post_code(0x25)
- /* Set Cache-as-RAM base address. */
+ /* Set code caching up for romstage. */
movl $(MTRRphysBase_MSR(1)), %ecx
- movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+ movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
wrmsr
movl $(MTRRphysMask_MSR(1)), %ecx
- movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+ movl $(CODE_CACHE_MASK | MTRRphysMaskValid), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr
