| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <AGESA.h> |
| #include <northbridge/amd/pi/agesawrapper.h> |
| |
| |
| static const PCIe_PORT_DESCRIPTOR PortList[] = { |
| { |
| 0, |
| PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), |
| PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, |
| HotplugDisabled, |
| PcieGenMaxSupported, |
| PcieGenMaxSupported, |
| AspmDisabled, 0x01, 0) |
| }, |
| /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ |
| { |
| 0, |
| PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), |
| PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, |
| HotplugDisabled, |
| PcieGenMaxSupported, |
| PcieGenMaxSupported, |
| AspmDisabled, 0x02, 0) |
| }, |
| /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ |
| { |
| 0, |
| PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), |
| PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, |
| HotplugDisabled, |
| PcieGenMaxSupported, |
| PcieGenMaxSupported, |
| AspmDisabled, 0x03, 0) |
| }, |
| /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ |
| { |
| 0, |
| PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), |
| PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, |
| HotplugDisabled, |
| PcieGenMaxSupported, |
| PcieGenMaxSupported, |
| AspmDisabled, 0x04, 0) |
| }, |
| /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ |
| { |
| DESCRIPTOR_TERMINATE_LIST, |
| PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), |
| PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, |
| HotplugDisabled, |
| PcieGenMaxSupported, |
| PcieGenMaxSupported, |
| AspmDisabled, 0x05, 0) |
| } |
| }; |
| |
| static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { |
| .Flags = DESCRIPTOR_TERMINATE_LIST, |
| .SocketId = 0, |
| .PciePortList = PortList, |
| .DdiLinkList = NULL, |
| }; |
| |
| /*---------------------------------------------------------------------------------------*/ |
| /** |
| * OemCustomizeInitEarly |
| * |
| * Description: |
| * This stub function will call the host environment through the binary block |
| * interface (call-out port) to provide a user hook opportunity |
| * |
| * Parameters: |
| * @param[in] *InitEarly |
| * |
| * @retval VOID |
| * |
| **/ |
| /*---------------------------------------------------------------------------------------*/ |
| VOID |
| OemCustomizeInitEarly ( |
| IN OUT AMD_EARLY_PARAMS *InitEarly |
| ) |
| { |
| InitEarly->GnbConfig.PcieComplexList = &PcieComplex; |
| InitEarly->PlatformConfig.CStateMode = CStateModeC6; |
| InitEarly->PlatformConfig.CpbMode = CpbModeAuto; |
| } |