src/drivers/intel/fsp2_0/Kconfig

# SPDX-License-Identifier: GPL-2.0-only

config PLATFORM_USES_FSP2_0
	bool
	default n
	help
	  Include FSP 2.0 wrappers and functionality

config PLATFORM_USES_FSP2_1
	bool
	default n
	select PLATFORM_USES_FSP2_0
	select FSP_USES_CB_STACK
	help
	  Include FSP 2.1 wrappers and functionality.
	  Feature added into FSP 2.1 specification that impacts coreboot is:
	  1. Remove FSP stack switch and use the same stack with boot firmware

config PLATFORM_USES_FSP2_2
	bool
	default n
	select PLATFORM_USES_FSP2_1
	help
	  Include FSP 2.2 wrappers and functionality.
	  Features added into FSP 2.2 specification that impact coreboot are:
	  1. Added multi-phase silicon initialization to increase the modularity of the
	      FspSiliconInit() API
	  2. FSP_INFO_HEADER changes to add FspMultiPhaseSiInitEntryOffset
	  3. Added EnableMultiPhaseSiliconInit, bootloaders designed for FSP2.0/2.1 can disable
	      the FspMultiPhaseSiInit() API and continue to use FspSiliconInit() without change.

if PLATFORM_USES_FSP2_0

config HAVE_INTEL_FSP_REPO
	bool
	help
	  Select this, if the FSP binaries for the platform are public
	  and available in 3rdparty/fsp/. When selecting this option, the
	  platform must also set FSP_HEADER_PATH and FSP_FD_PATH correctly.

config FSP_USE_REPO
	bool "Use binaries of the Intel FSP repository on GitHub"
	depends on HAVE_INTEL_FSP_REPO
	default y
	help
	  Select this option to use the default FSP headers and binaries
	  found in the IntelFsp GitHub repository at

	    https://github.com/IntelFsp/FSP/

	  If unsure, say Y.

config FSP_HEADER_PATH
	string "Location of FSP headers" if !FSP_USE_REPO
	help
	  Include directory with the FSP ABI header files.

config FSP_FD_PATH
	string
	depends on FSP_USE_REPO
	help
	  Path to the FSP FD file that contains the individual FSP-T, FSP-M
	  and FSP-S binaries.

config ADD_FSP_BINARIES
	bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO
	default y if FSP_USE_REPO
	help
	  Add the FSP-M and FSP-S binaries to CBFS.

config FSP_T_CBFS
	string "Name of FSP-T in CBFS"
	depends on FSP_CAR
	default "fspt.bin"

config FSP_S_CBFS
	string "Name of FSP-S in CBFS"
	default "fsps.bin"

config FSP_M_CBFS
	string "Name of FSP-M in CBFS"
	default "fspm.bin"

config FSP_T_FILE
	string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_USE_REPO
	depends on ADD_FSP_BINARIES
	depends on FSP_CAR
	default "\$(obj)/Fsp_T.fd" if FSP_USE_REPO
	help
	  The path and filename of the Intel FSP-T binary for this platform.

config FSP_M_FILE
	string "Intel FSP-M (memory init) binary path and filename" if !FSP_USE_REPO
	depends on ADD_FSP_BINARIES
	default "\$(obj)/Fsp_M.fd" if FSP_USE_REPO
	help
	  The path and filename of the Intel FSP-M binary for this platform.

config FSP_S_FILE
	string "Intel FSP-S (silicon init) binary path and filename" if !FSP_USE_REPO
	depends on ADD_FSP_BINARIES
	default "\$(obj)/Fsp_S.fd" if FSP_USE_REPO
	help
	  The path and filename of the Intel FSP-S binary for this platform.

config FSP_CAR
	bool
	default n
	help
	  Use FSP APIs to initialize & Tear Down the Cache-As-Ram

config FSP_M_XIP
	bool
	default n
	help
	  Select this value when FSP-M is execute-in-place.

config FSP_T_XIP
	bool
	default n
	help
	  Select this value when FSP-T is execute-in-place.

config FSP_USES_CB_STACK
	bool
	default n
	help
	  Enable support for fsp to use same stack as coreboot.
	  This option allows fsp to continue using coreboot stack
	  without reinitializing stack pointer. This feature is
	  supported Icelake onwards.

config FSP_TEMP_RAM_SIZE
	hex
	help
	  The amount of memory coreboot reserves for the FSP to use. In the
	  case of FSP 2.1 and newer that share the stack with coreboot instead
	  of having its own stack, this is the amount of anticipated heap usage
	  in CAR by FSP to setup HOB and needs to be the recommended value from
	  the Platform FSP integration guide. In the case of the FSP having its
	  own stack that will be placed in DRAM and not in CAR, this is the
	  amount of memory the FSP needs for its stack and heap.

config FSP2_0_USES_TPM_MRC_HASH
	bool
	depends on TPM1 || TPM2
	depends on VBOOT && VBOOT_STARTS_IN_BOOTBLOCK
	default y if HAS_RECOVERY_MRC_CACHE
	default n
	select VBOOT_HAS_REC_HASH_SPACE
	help
	  Store hash of trained recovery MRC cache in NVRAM space in TPM.
	  Use the hash to validate recovery MRC cache before using it.
	  This hash needs to be updated every time recovery mode training
	  is recomputed, or if the hash does not match recovery MRC cache.
	  Selecting this option requires that TPM already be setup by this
	  point in time.  Thus it is only compatible when the option
	  VBOOT_STARTS_IN_BOOTBLOCK is selected, which causes verstage and
	  TPM setup to occur prior to memory initialization.

config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
	bool
	help
	  This is selected by SoC or mainboard to supply their own
	  concept of a version for the memory settings respectively.
	  This allows deployed systems to bump their version number
	  with the same FSP which will trigger a retrain of the memory.

config FSP_PEIM_TO_PEIM_INTERFACE
	bool
	select FSP_USES_MP_SERVICES_PPI
	help
	  This option allows SOC user to create specific PPI for Intel FSP
	  usage, coreboot will provide required PPI structure definitions
	  along with all APIs as per EFI specification. So far this feature
	  is limited till EFI_PEI_MP_SERVICE_PPI and this option might be
	  useful to add further PPI if required.

config HAVE_FSP_LOGO_SUPPORT
	bool
	default n

config FSP2_0_DISPLAY_LOGO
	bool "Enable logo"
	default n
	depends on HAVE_FSP_LOGO_SUPPORT
	help
	  Uses the FSP to display the boot logo. This method supports a
	  BMP file only. The uncompressed size can be up to 1 MB. The logo can be compressed
	  using LZMA.

config FSP2_0_LOGO_FILE_NAME
	string "Logo file"
	depends on FSP2_0_DISPLAY_LOGO
	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"

config FSP_COMPRESS_FSP_S_LZMA
	bool

config FSP_COMPRESS_FSP_S_LZ4
	bool

config FSP_COMPRESS_FSP_M_LZMA
	bool
	depends on !FSP_M_XIP

config FSP_COMPRESS_FSP_M_LZ4
	bool
	depends on !FSP_M_XIP

config FSP_M_ADDR
	hex
	help
	  The address FSP-M will be relocated to during build time

config FSP_STATUS_GLOBAL_RESET_REQUIRED_3
	bool
	help
	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_4
	bool
	help
	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_5
	bool
	help
	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_6
	bool
	help
	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_7
	bool
	help
	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_8
	bool
	help
	  FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET
	hex
	default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3
	default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4
	default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5
	default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6
	default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7
	default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8
	default 0xffffffff
	help
	  If global reset is supported by SoC then select the correct status value for global
	  reset type from SoC Kconfig based on available Kconfig options
	  FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported.

if FSP_PEIM_TO_PEIM_INTERFACE
source "src/drivers/intel/fsp2_0/ppi/Kconfig"
endif

endif