src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS
is by default GEN1 and ThP has bad synchronization on polarity
inversion. When the root port request for speed change, ThP doesn’t
confirm the request, and both sides are moving to polling after
timeout, hot reset is issued, and then most of the CFG space is
initialized. From the observation, CCC/ECPM/LTR would be reset to
default but CCC/ECPM of root port and end devices have been
reconfigured in pci_scan. The LTR configuration for root port
is still missing.
BUG=b:117618636
BRANCH=None
TEST=Warm/cold reset for 10 times and didn't see unsupported request
related AER error messages & $lspci -vvs 00:1c.0|grep LTR and
ensure LTR+ is presenti & $iotools pci_read32 0 0x1c 0 0x68
and ensure bit10 is set.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/30486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Reviewed-on: https://chromium-review.googlesource.com/c/1407535
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Commit-Queue: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index e197114..01a338d 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -255,9 +255,34 @@
}
#endif
+static void pci_dev_apply_quirks(struct device *dev)
+{
+ unsigned int cap;
+ uint16_t val;
+ struct device *root = dev->bus->dev;
+
+ switch (dev->device) {
+ case PCI_DEVICE_ID_TP_9260_SERIES_WIFI:
+ cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
+ /* Check the LTR for root port and enable it */
+ if (cap) {
+ val = pci_read_config16(root, cap +
+ PCI_EXP_DEV_CAP2_OFFSET);
+ if (val & LTR_MECHANISM_SUPPORT) {
+ val = pci_read_config16(root, cap +
+ PCI_EXP_DEV_CTL_STS2_CAP_OFFSET);
+ val |= LTR_MECHANISM_EN;
+ pci_write_config16(root, cap +
+ PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, val);
+ }
+ }
+ }
+}
+
static void wifi_pci_dev_init(struct device *dev)
{
pci_dev_init(dev);
+ pci_dev_apply_quirks(dev);
if (IS_ENABLED(CONFIG_ELOG)) {
uint32_t val;
