UPSTREAM: src: Replace MSR addresses with macros
BUG=none
BRANCH=none
TEST=none
Change-Id: I51f0351f76328724e377839b7ef1670a6222cac3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 603963e1ba4147ef31a72b94304708ab416e3b6a
Original-Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a
Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Original-Reviewed-on: https://review.coreboot.org/28784
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://chromium-review.googlesource.com/1277640
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 6034235..ae34347 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -102,7 +102,7 @@
msr.lo = (unsigned long)m + sizeof(struct microcode);
msr.hi = 0;
- wrmsr(0x79, msr);
+ wrmsr(IA32_BIOS_UPDT_TRIG, msr);
#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "microcode: updated to revision "
@@ -158,12 +158,12 @@
return NULL;
#endif
- /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
+ /* CPUID sets MSR 0x8B if a microcode update has been loaded. */
msr.lo = 0;
msr.hi = 0;
- wrmsr(0x8B, msr);
+ wrmsr(IA32_BIOS_SIGN_ID, msr);
eax = cpuid_eax(1);
- msr = rdmsr(0x8B);
+ msr = rdmsr(IA32_BIOS_SIGN_ID);
rev = msr.hi;
x86_model = (eax >> 4) & 0x0f;
x86_family = (eax >> 8) & 0x0f;
@@ -171,7 +171,7 @@
pf = 0;
if ((x86_model >= 5) || (x86_family > 6)) {
- msr = rdmsr(0x17);
+ msr = rdmsr(IA32_PLATFORM_ID);
pf = 1 << ((msr.hi >> 18) & 7);
}
#if !defined(__ROMCC__)
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 5b73844..04ef3d5 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -50,9 +50,9 @@
microcode_ver.lo = 0;
microcode_ver.hi = 0;
- wrmsr(0x8B, microcode_ver);
+ wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1);
- microcode_ver = rdmsr(0x8b);
+ microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpuidr.eax, microcode_ver.hi, cpu_name);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c
index fc8b37c..44a3d27 100644
--- a/src/soc/intel/broadwell/romstage/report_platform.c
+++ b/src/soc/intel/broadwell/romstage/report_platform.c
@@ -113,9 +113,9 @@
microcode_ver.lo = 0;
microcode_ver.hi = 0;
- wrmsr(0x8B, microcode_ver);
+ wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1);
- microcode_ver = rdmsr(0x8b);
+ microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index a652b52..b59d351 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -145,9 +145,9 @@
microcode_ver.lo = 0;
microcode_ver.hi = 0;
- wrmsr(0x8B, microcode_ver);
+ wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
cpuidr = cpuid(1);
- microcode_ver = rdmsr(0x8b);
+ microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
/* Look for string to match the name */
for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
