| /include/ "skeleton.dtsi" |
| |
| / { |
| model = "NVIDIA Tegra 250"; |
| compatible = "nvidia,tegra250"; |
| interrupt-parent = <&intc>; |
| |
| amba { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| intc: interrupt-controller@50041000 { |
| compatible = "nvidia,tegra250-gic", "arm,gic"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| reg = < 0x50041000 0x1000 >, |
| < 0x50040100 0x0100 >; |
| }; |
| }; |
| |
| pllp: clock0 { |
| compatible = "nvidia,tegra20-pll-sys"; |
| #clock-cells = <1>; |
| clock-frequency = <216000000>; |
| clock-output-names = "pllp"; |
| }; |
| |
| /* TBD: provides an easy way to find clocks for now */ |
| clocks { |
| compatible = "board-clocks"; |
| pllp = <&pllp>; |
| }; |
| |
| gpio: gpio@6000d000 { |
| compatible = "nvidia,tegra250-gpio", "ns16550"; |
| reg = < 0x6000d000 0x1000 >; |
| interrupts = < 64 65 66 67 87 119 121 >; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| serial@70006000 { |
| compatible = "nvidia,tegra250-uart", "ns16550"; |
| reg = <0x70006000 0x40>; |
| id = <0>; |
| reg-shift = <2>; |
| interrupts = < 68 >; |
| status = "disabled"; |
| }; |
| |
| serial@70006040 { |
| compatible = "nvidia,tegra250-uart", "ns16550"; |
| reg = <0x70006040 0x40>; |
| id = <1>; |
| reg-shift = <2>; |
| interrupts = < 69 >; |
| status = "disabled"; |
| }; |
| |
| serial@70006200 { |
| compatible = "nvidia,tegra250-uart", "ns16550"; |
| reg = <0x70006200 0x100>; |
| id = <2>; |
| reg-shift = <2>; |
| interrupts = < 78 >; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@70006300 { |
| compatible = "nvidia,tegra250-uart", "ns16550"; |
| reg = <0x70006300 0x100>; |
| id = <3>; |
| reg-shift = <2>; |
| interrupts = < 122 >; |
| status = "disabled"; |
| }; |
| |
| serial@70006400 { |
| compatible = "nvidia,tegra250-uart", "ns16550"; |
| reg = <0x70006400 0x100>; |
| id = <4>; |
| reg-shift = <2>; |
| interrupts = < 123 >; |
| status = "disabled"; |
| }; |
| |
| sdhci@c8000000 { |
| compatible = "nvidia,tegra250-sdhci"; |
| reg = <0xc8000000 0x200>; |
| interrupts = <46>; |
| periph-id = <14>; // PERIPH_ID_SDMMC1 |
| status = "disabled"; |
| }; |
| |
| sdhci@c8000200 { |
| compatible = "nvidia,tegra250-sdhci"; |
| reg = <0xc8000200 0x200>; |
| interrupts = <47>; |
| periph-id = <9>; // PERIPH_ID_SDMMC2 |
| status = "disabled"; |
| }; |
| |
| sdhci@c8000400 { |
| compatible = "nvidia,tegra250-sdhci"; |
| reg = <0xc8000400 0x200>; |
| interrupts = <51>; |
| periph-id = <69>; // PERIPH_ID_SDMMC3 |
| status = "disabled"; |
| }; |
| |
| sdhci@c8000600 { |
| compatible = "nvidia,tegra250-sdhci"; |
| reg = <0xc8000600 0x200>; |
| interrupts = <63>; |
| periph-id = <15>; // PERIPH_ID_SDMMC4 |
| status = "disabled"; |
| }; |
| |
| pwfm0: pwm@7000a000 { |
| compatible = "nvidia,tegra250-sdhci"; |
| reg = <0x7000a000 0x4>; |
| status = "disabled"; |
| }; |
| |
| pwfm1: pwm@7000a010 { |
| compatible = "nvidia,tegra250-sdhci"; |
| reg = <0x7000a010 0x4>; |
| status = "disabled"; |
| }; |
| |
| pwfm2: pwm@7000a020 { |
| compatible = "nvidia,tegra250-sdhci"; |
| reg = <0x7000a020 0x4>; |
| status = "disabled"; |
| }; |
| |
| pwfm3: pwm@7000a030 { |
| compatible = "nvidia,tegra250-sdhci"; |
| reg = <0x7000a030 0x4>; |
| status = "disabled"; |
| }; |
| |
| display1: display@0x54200000 { |
| compatible = "nvidia,tegra250-display"; |
| reg = <0x54200000 0x40000>; |
| status = "disabled"; |
| }; |
| |
| /* This table has USB timing parameters for each Oscillator frequency we |
| * support. There are four sets of values: |
| * |
| * 1. PLLU configuration information (reference clock is osc/clk_m and |
| * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). |
| * |
| * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz |
| * ---------------------------------------------------------------------- |
| * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) |
| * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) |
| * Filter frequency (MHz) 1 4.8 6 2 |
| * CPCON 1100b 0011b 1100b 1100b |
| * LFCON0 0 0 0 0 |
| * |
| * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: |
| * |
| * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz |
| * --------------------------------------------------------------------------- |
| * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) |
| * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) |
| * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) |
| * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) |
| * |
| * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and |
| * SessEnd. Each of these signals have their own debouncer and for each of |
| * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or |
| * BIAS_DEBOUNCE_B). |
| * |
| * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: |
| * 0xffff -> No debouncing at all |
| * <n> ms = <n> *1000 / (1/19.2MHz) / 4 |
| * |
| * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: |
| * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 |
| * |
| * We need to use only DebounceA for BOOTROM. We dont need the DebounceB |
| * values, so we can keep those to default. |
| * |
| * a4. The 20 microsecond delay after bias cell operation. |
| * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz |
| */ |
| usbparams@0 { |
| compatible = "nvidia,tegra250-usbparams"; |
| osc-frequency = <13000000>; |
| /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ |
| params = <0x3c0 0x0d 0x00 0xc 0 0x02 0x33 0x05 0x7f 0x7ef4 5>; |
| }; |
| |
| usbparams@1 { |
| compatible = "nvidia,tegra250-usbparams"; |
| osc-frequency = <19200000>; |
| params = <0x0c8 0x04 0x00 0x3 0 0x03 0x4b 0x06 0xbb 0xbb80 7>; |
| }; |
| |
| usbparams@2 { |
| compatible = "nvidia,tegra250-usbparams"; |
| osc-frequency = <12000000>; |
| params = <0x3c0 0x0c 0x00 0xc 0 0x02 0x2f 0x04 0x76 0x7530 5>; |
| }; |
| |
| usbparams@3 { |
| compatible = "nvidia,tegra250-usbparams"; |
| osc-frequency = <26000000>; |
| params = <0x3c0 0x1a 0x00 0xc 0 0x04 0x66 0x09 0xfe 0xfde8 9>; |
| }; |
| |
| usb@0xc5008000 { |
| compatible = "nvidia,tegra250-usb"; |
| reg = <0xc5008000 0x8000>; |
| periph-id = <59>; // PERIPH_ID_USB3 |
| status = "disabled"; |
| }; |
| |
| usb@0xc5000000 { |
| compatible = "nvidia,tegra250-usb"; |
| reg = <0xc5000000 0x8000>; |
| periph-id = <22>; // PERIPH_ID_USBD |
| status = "disabled"; |
| }; |
| |
| kbc@0x7000e200 { |
| compatible = "nvidia,tegra250-kbc"; |
| reg = <0x7000e200 0x0078>; |
| }; |
| |
| i2c@0x7000c000 { |
| compatible = "nvidia,tegra250-i2c"; |
| reg = <0x7000c000 0x006c>; |
| pinmux = <1>; |
| speed = <100000>; |
| periph-id = <12>; // PERIPH_ID_I2C1 |
| }; |
| |
| i2c@0x7000c400 { |
| compatible = "nvidia,tegra250-i2c"; |
| reg = <0x7000c400 0x006c>; |
| pinmux = <2>; |
| speed = <100000>; |
| periph-id = <54>; // PERIPH_ID_I2C2 |
| }; |
| |
| i2c@0x7000c500 { |
| compatible = "nvidia,tegra250-i2c"; |
| reg = <0x7000c500 0x006c>; |
| pinmux = <1>; |
| speed = <100000>; |
| periph-id = <67>; // PERIPH_ID_I2C3 |
| }; |
| |
| i2c@0x7000d000 { |
| compatible = "nvidia,tegra250-i2c"; |
| reg = <0x7000d000 0x007c>; |
| pinmux = <1>; |
| speed = <100000>; |
| use-dvc-ctlr; |
| periph-id = <47>; // PERIPH_ID_DVC_I2C |
| }; |
| |
| nand: nand-controller@0x70008000 { |
| compatible = "nvidia,tegra2-nand"; |
| reg = <0x70008000 0x100>; |
| status = "disabled"; |
| }; |
| }; |